GithubAamna/Minimal-Core-Self-Designed-Processor-using-Verilog-HDL

Language: Verilog - Size: 83 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

GithubAamna/4-bit-Ripple-Carry-Adder-using-full-adders

A ripple carry adder constituted of full adders to add two 4 bit inputs.

Language: Verilog - Size: 104 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

GithubAamna/GithubAamna

My Personal Repository

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GithubAamna/SQL-Data-Cleaning---A-Beginner-Project

Used SQL on mySQL Workbench to clean data and visualized the results on Tableau.

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GithubAamna/SQL-Basics

Size: 476 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0