GitHub / Elzawawy / mips-processor-simulator
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
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Stars: 2
Forks: 3
Open issues: 0
License: mit
Language: SystemVerilog
Size: 1.05 MB
Dependencies parsed at: Pending
Created at: almost 5 years ago
Updated at: almost 2 years ago
Pushed at: almost 5 years ago
Last synced at: almost 2 years ago
Topics: mips, mips-architecture, mips-simulator, multi-cycle-processor, pipelined-processors, single-cycle-processor