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GitHub / ShyavanS / Sequential-Logic-Finite-State-Machine-Design-Project

Final design project for an Engineering Physics course at McMaster University. A finite-state machine that was designed using the ICs available to us and NI Multisim to produce a device that cycled through a student number on a 7-segment display demonstrating knowledge of sequential logic.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ShyavanS%2FSequential-Logic-Finite-State-Machine-Design-Project

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Forks: 0
Open issues: 0

License: gpl-3.0
Language:
Size: 568 KB
Dependencies parsed at: Pending

Created at: 11 months ago
Updated at: 11 months ago
Pushed at: 11 months ago
Last synced at: 11 months ago

Topics: circuit-design, design-project, engineering-physics, finite-state-machine, multisim, sequential-logic, university-course, university-project

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