GitHub / electricalgorithm / introduction-to-VHDL-projects
VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.
Stars: 1
Forks: 0
Open issues: 0
License: None
Language: VHDL
Size: 661 KB
Dependencies parsed at: Pending
Created at: almost 3 years ago
Updated at: over 2 years ago
Pushed at: almost 3 years ago
Last synced at: about 2 years ago
Topics: adder-circuit, chip-design, comparator, digtial-design, four-digit-seven-segment-driver, line-buffer, mux, ring-counter, seven-segment, traffic-light-controller