GitHub / nelsoncsc / basicSV
Very basic SystemVerilog examples
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Forks: 0
Open issues: 0
License: mit
Language: SystemVerilog
Size: 1.29 MB
Dependencies parsed at: Pending
Created at: over 8 years ago
Updated at: almost 3 years ago
Pushed at: about 8 years ago
Last synced at: about 2 years ago
Topics: basics, examples, systemverilog-hdl
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