GitHub / ninja3011 / riscv-cpu-core
A pipelined RISC-V CPU Core Implemented in Makerchip using TL-Verilog
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Stars: 6
Forks: 1
Open issues: 1
License: None
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Size: 4.73 MB
Dependencies parsed at: Pending
Created at: almost 4 years ago
Updated at: about 2 years ago
Pushed at: about 3 years ago
Last synced at: over 1 year ago
Topics: circuit-design, gnu-toolchain, makerchip, risc-v, tl-verilog
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