GitHub topics: control-unit

Repositories

arasgungore/NandGame

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

Size: 4.85 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 1

mck-sbs/PyConSys

Python Control System : Create control loops and let the AI set the PID parameters

Language: Python - Size: 7.25 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 33 - Forks: 10

Karan-nevage/RISC-V-Single-Cycle-Core-Verilog-

This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.

Language: JavaScript - Size: 1.07 MB - Last synced at: 3 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 1

mehmetakifkoz/MARS-Web-App

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

Language: JavaScript - Size: 25.4 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

DoniaGameel/Pipelined-Processor-using-verilog

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

Language: Verilog - Size: 891 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

NajimAlfutini/Design-A-Full-SRC-Processor

The project involves designing a Simple RISC Computer (SRC) processor with 23 instructions, 32 registers, a control unit, data path, and memory components, aiming to create a functional CPU architecture capable of executing instructions.

Language: HTML - Size: 4.5 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

keonhee-han/Control-Unit-Design-VHDL-

Size: 12.9 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

mck-sbs/Pendulum

Inverted Pendulum in python with pybox2d. Fuzzy and PID simulation included.

Language: Python - Size: 5.1 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2

ryanvickr/Taillight-Control-Unit

An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.

Language: VHDL - Size: 17.6 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

gabrielganzer/VHDL-DesignSynthesis

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

Language: Verilog - Size: 7.4 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0

beyzanc/18-bit-processor-implementation-using-logisim

18-bit processor implementation using Logisim

Language: Python - Size: 530 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

AbdullahSh20/BLG222E

Istanbul Technical University's Computer Organization course projects for the year 2023

Language: Verilog - Size: 3.7 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

0marAmr/Single_Cycle_RISC-V_processor

Language: Verilog - Size: 563 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

suly520/VisuProject

Software for 3-axis machine control. It uses a Raspberry Pi with motor controllers and additional electronics. Features: visualization, GPIO emulation, touchscreen capability, and Cython optimization. Tested on Windows(visu) and Raspberry Pi OS. Under development with Pyside2 and OpenGl.

Language: Python - Size: 26 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

EslamAsHhraf/Pipelined-Processor

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

Language: Verilog - Size: 864 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0