Topic: "opencomputeproject"
chipsalliance/caliptra-ss
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
Language: SystemVerilog - Size: 19.5 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 20 - Forks: 19
rivosinc/scampi
DC-SCMv2 dual-node card
Size: 2.06 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 0 - Forks: 0
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