Topic: "questasim"
suoto/hdl_checker
Repurposing existing HDL tools to help writing better code
Language: Python - Size: 1.05 MB - Last synced at: 6 months ago - Pushed at: 11 months ago - Stars: 192 - Forks: 22
Paebbels/JSON-for-VHDL
A JSON library implemented in VHDL.
Language: VHDL - Size: 138 KB - Last synced at: 28 days ago - Pushed at: over 2 years ago - Stars: 78 - Forks: 17
MJoergen/HyperRAM
Portable HyperRAM controller
Language: VHDL - Size: 4.2 MB - Last synced at: 4 days ago - Pushed at: 5 months ago - Stars: 54 - Forks: 14
wyvernSemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
Language: VHDL - Size: 2.71 MB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 22 - Forks: 3
Ghonimo/Pre_Silicon-AHB-to_APB-Verification
Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
Language: SystemVerilog - Size: 13.5 MB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 22 - Forks: 6
Paebbels/pyIPCMI
A Python-based IP Core Management Infrastructure.
Language: Python - Size: 578 KB - Last synced at: 28 days ago - Pushed at: about 4 years ago - Stars: 8 - Forks: 6
MJoergen/Avalon
Utilities for Avalon Memory Map
Language: VHDL - Size: 1020 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 7 - Forks: 0
yuravg/eda-scripts
Collection of scripts for EDA tools
Language: Shell - Size: 185 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 6 - Forks: 2
htminuslab/Modelsim-Unicorn
Modelsim QEMU Unicorn integration via the FLI
Language: C - Size: 21.9 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 0
dave2pi/SublimeLinter-contrib-vlog
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
Language: Python - Size: 5.86 KB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 6 - Forks: 1
edaa-org/pyEDAA.ToolSetup
Language: Python - Size: 2.84 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 5 - Forks: 0
WajahatRiaz/QuadSPI
RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
Language: SystemVerilog - Size: 1.34 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1
yuravg/color_questasim
A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.
Language: Perl - Size: 185 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 4 - Forks: 0
jevogel/SublimeLinter-contrib-modelsim Fork of SublimeLinter/SublimeLinter-template
⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.
Language: Python - Size: 23.4 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 2
Abdelrahman1810/SPI_Slave_with_Single_Port_RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Language: Verilog - Size: 401 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0
sbaldzenka/uart_core
UART IP-core for FPGA.
Language: VHDL - Size: 26.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
NikosDelijohn/finjenv
Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator
Language: Verilog - Size: 599 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0
teekamkhandelwal/SRAM_Controller
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
Language: Verilog - Size: 72.3 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0
Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
Language: Verilog - Size: 30.2 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0
cad-polito-it/r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
Language: Verilog - Size: 4.07 MB - Last synced at: about 1 month ago - Pushed at: 12 months ago - Stars: 1 - Forks: 1
AlPrime2k1/Finite-State-Machines
Latest addition to REPO : Folder with vending machine design and TB including code coverage report
Language: HTML - Size: 358 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
aaronrjmanj/verilog
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ [email protected]
Language: Verilog - Size: 567 KB - Last synced at: 11 months ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
teekamkhandelwal/Uart_tx_main
Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate through digital pin 0, digital pin 1.
Language: Verilog - Size: 17.6 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
kropotin4/SystemVerilog-examples
Попытка написать несколько примеров кода на языке SystemVerilog.
Language: SystemVerilog - Size: 25.4 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0
dave2pi/SublimeLinter-contrib-vcom
SublimeLinter plugin for linting VHDL with Modelsim vcom
Language: Python - Size: 5.86 KB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0
Azrielx86/LaboratorioOAC2025-2
Prácticas de laboratorio para el laboratorio de Organización y Arquitectura de Computadoras - Semestre 2025-2
Language: VHDL - Size: 1.03 MB - Last synced at: 7 days ago - Pushed at: 22 days ago - Stars: 0 - Forks: 0
BakxY/VHDL-QQS
VS Code extension for Intel Quartus: seamless project compilation, direct access to the Quartus programmer and RTL viewer, automated testbench generation for QuestaSim, integrated QuestaSim simulation, streamlined project configuration, direct file management, top-level entity changes, and on-demand source file formatting.
Language: TypeScript - Size: 806 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0
Abdelrahman1810/RTL-Verification-of-AMBA3_4-APB-Protocol
This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.
Language: SystemVerilog - Size: 2.98 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
flfl04/UART_Verilog
UART 8-Bit Verilog Simple Realization
Language: Verilog - Size: 18.6 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
Abdelrahman1810/SPI-Slave-with-Single-Port-RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Language: Verilog - Size: 600 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
hcshires/MIPS-Processors
CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations
Language: Python - Size: 22.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
lazarvulic99/SystemVerilog-Verification---Register-functionalities
Simple register realisation for SystemVerilog Verification
Language: SystemVerilog - Size: 1.65 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0
