Topic: "risc-vcore"
ShonTaware/RISC-V_Core_4_Stage
RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set
Size: 3.07 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 4
LeviBohnacker/EDRICO
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and implement modern processor architectures.
Language: VHDL - Size: 23.7 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 2
