Aom92/FPGA-Effects-Pedal

Proyecto de Tesis donde se realiza procesamiento digital de audio para hacer una pedalera de efectos de guitarra con la FPGA DE10-Lite

Language: Jupyter Notebook - Size: 210 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

mazen-daghari/VHDL-AMS-Sonde

description d'un capteur ECG a base de VHDL-AMS (SIMPLORER V7)

Language: Brightscript - Size: 1.95 MB - Last synced at: 17 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

alessda/door_lock

Language: C - Size: 1.56 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

AzazHassankhan/FPGA_Building_Blocks_VHDL

Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐

Size: 182 KB - Last synced at: 4 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

onegentig/VUT-FIT-INP2022-projekt1 📦

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 2.42 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

seigtm/circuitry-spbpu-homework

This repository is dedicated to storing and managing homework assignments for the course "Digital Circuit Design: Modeling and Description Languages." The assignments primarily involve VHDL source code.

Language: VHDL - Size: 8.79 KB - Last synced at: 9 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

farbodfld/CoDesign-Course

Projects of CoDesign course at SBU

Language: VHDL - Size: 3.86 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

francescospangaro/ProgettoRL

Prova finale di Reti Logiche A.A. 2022/2023

Language: VHDL - Size: 5.33 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

IgnacioChirinos/MIPS-VHDL-Vivado

MIPS processor that performs matrix multiplication 3x3 based on VHDL and implemented in XILINX

Language: VHDL - Size: 296 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

hk-117/VHDL

Some example of vhdl code, using ghdl and gtkwave.

Language: VHDL - Size: 30.3 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

jhenals/VHDL-Code---Circuito-Sequenziale

Secondo Progetto di Elettronico Digitale AA2022-2023

Size: 4.33 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

jhenals/VHDL-Code---Carry-Select-32bit

Progetto di Elettronica Digitale AA 2022-2023

Size: 4.67 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Stavros/LedToggle

An example for NIOS II processor to toggle a Led with a Button

Language: Verilog - Size: 13.2 MB - Last synced at: 4 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 1

AndreaNeti/Progetto-Reti-Logiche-2022

Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - a.a. 2021-2022

Language: VHDL - Size: 835 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

aliansgp/VHDL_Adders

Different adders code in VHDL and Comparison

Language: C - Size: 1.3 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

aliansgp/VHDL_Multipliers

Different Multipliers code in VHDL and Comparison

Language: C - Size: 1.35 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

DoCodeForever/vhdl

Size: 535 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

chclau/par2ser

Language: VHDL - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

hussainmansour/4-bit-BCD-Counter

implementation of 4-bit BCD up/down counter. The counter work as follows: ● If input X = 0, the counter counts up. Otherwise, it counts down. ● If counting up, the counter’s value should be: 0000, 0001, 0010... ● If counting down: 0010, 0001, 0000...

Language: VHDL - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

rajsinghtech/MIPS-Pipelined-Processor

CPRE 381 Project 2 Pipelined Processor - Both hardware and software

Language: HTML - Size: 123 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

chclau/vhdl_arbiter

VHDL arbiter. Fixed witdh, fixed priority

Language: VHDL - Size: 21.5 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

LucaLombardini/fft_sylvester_ii

Development and Testing of an Hardware achitecture dedicate to the FFT calculus based on Cooley-Tuckey's Algorithm

Language: VHDL - Size: 9.57 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

MostafaGalal1/Full-Adder-Subtractor

4-bit ripple adder, which adds 2 4-bit inputs introducing sum and carry signals and implementing. 1. Half adder. 2. Full adder using the half adder. 3. 4-bit ripple adder/subtractor using the full adder.

Language: VHDL - Size: 16.6 KB - Last synced at: 8 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

MostafaGalal1/4-bit_BCD_counter

implementation of 4-bit BCD up/down counter. The counter work as follows: ● If input X = 0, the counter counts up. Otherwise, it counts down. ● If counting up, the counter’s value should be: 0000, 0001, 0010... ● If counting down: 0010, 0001, 0000...

Language: VHDL - Size: 16.6 KB - Last synced at: 8 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

ads930/Thermostat

This is the code for the multiple implementations of a finite state machine thermostat. There is an implementation in C for the dsPIC33EP64MC502, an implementation with VHDL, and an implementation with LabVIEW and DAQmx. TwithFPO_DAQmx.vi requires a MyDAQ to run the program.

Language: C - Size: 82 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

iremersin/HomeAutomation

Basic home automation process in VHDL.

Language: VHDL - Size: 2.93 KB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

mtzor/PipelineProcessor

This is a basic pipeline processor implemented in VHDL

Language: VHDL - Size: 607 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

andrevale99/CD_ELE2715

Language: VHDL - Size: 533 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Kanishk-K-U/ALU

Design of an arithmetic logic (ALU). It typically performs mathematical and logical functions. An ALU is designed and implemented using VHDL.

Language: VHDL - Size: 790 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

Confizolo/PoDProjects

Various projects for Physics of Data master degree

Language: Jupyter Notebook - Size: 348 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Jalundkvist/VHDL_Clock_school_project

Project for VHDL clock

Language: VHDL - Size: 2.74 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

ivochan/VHDL-Exercises

digital electronics components implementation in VHDL

Language: VHDL - Size: 41.6 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

metehancaliskan/Not-Hitting-The-Obstacles

This project is my digital electronics project and is based on VHDL.

Size: 938 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Sukhendu2002/coa-lab-vhdl-codes

Here you can find verious VHDL code with test banch

Language: VHDL - Size: 357 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

touunix/LED-display-control-VHDL

LED display control VHDL | Sterowanie wyświetlaczem LED VHDL

Language: VHDL - Size: 685 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

touunix/Simple-stopwatch-VHDL

Simple stopwatch VHDL | Prosty stoper VHDL

Language: VHDL - Size: 677 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

touunix/Gray-code-counter-VHDL

Gray code counter VHDL | Licznik w kodzie Graya VHDL

Language: VHDL - Size: 499 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

touunix/Frequency-divider-VHDL

Frequency divider VHDL | Dzielnik częstotliwości VHDL

Language: VHDL - Size: 481 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

touunix/MUX-VHDL

MUX VHDL | Układ kombinacyjny VHDL

Language: VHDL - Size: 681 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

touunix/Parity-generator-VHDL

Parity generator VHDL | Generator parzystości VHDL

Language: VHDL - Size: 670 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

talisma-cassoma/finite-state-machine-FSM

Moore and Mealy Machine architecture (model)

Language: VHDL - Size: 31.3 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

saibhargav1508/Basic-combinational-logic-VHDL

This repository contains synthesizable VHDL code for basic combinational logic circuits such as Adder with register, 2:4 decoder, 4:2 priority encoder, Multiplier with register and other circuits.

Language: VHDL - Size: 5.86 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

charrat0649/BE_VHDL_M2SME_Binome3

L’objectif de ce bureau d’étude est de concevoir le pilote de barre franche sous forme d’un système sur puce programmable SOPC (System On Programmable Chip) décrite à l’aide du langage de description de Hardware VHDL (Very High Speed Hardware Description Langage) en se basant sur l’analyse de spécifications et découpage fonctionnel du système choisi et la conception de circuits d’interfaces numériques en VHDL pour le simuler et le valider sur la maquette, puis faire des interfaçages avec les bus microprocesseur tels que NIOS, Altera, Avalon pour la validation du SOPC en manipulation.

Language: C - Size: 13.4 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

tristan-oa/ALU-in-VHDL

Building an ALU using VHDL

Size: 5.21 MB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

monicakarine/Pedagio

Projeto e simulação de um pedágio em VHDL para a disciplina de Laboratório de Sistemas Digitais da UFMG.

Language: VHDL - Size: 210 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

kevinkirsten/ControleSalaDeReunioesVHDL

Circuito de controle de sala de reuniões implementado em VHDL

Language: VHDL - Size: 4.37 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

aniekanBane/poly-eval-vhdl

Modelling and simulation of a polynomial evaluator in VHDL using stepwise refinement.

Language: VHDL - Size: 32.2 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

anuragmukherjee2001/VHDL-programming

Language: VHDL - Size: 1000 Bytes - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

hungrymonkey/i2c

1:1 i2c device written in VHDL

Language: VHDL - Size: 22.7 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

mustafa1728/Digital-Image-Filtering-VHDL

A VHDL description of a digital image filtering system on FPGAs. Part of COL215 course project.

Language: VHDL - Size: 3.3 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

eimon96/VHDL

Language: VHDL - Size: 342 KB - Last synced at: 8 months ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

Subhankar2000/Xilinx-ISE-8.2i-EC792-VLSI-LAB

saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)

Language: VHDL - Size: 13.8 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

aayushgoyal443/Image-Filter

An Image filter that takes in an image and applies the smoothening or sharpening filter on it depending on the user's choice.

Language: VHDL - Size: 813 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

minji-o-j/Device-Programming

[Spring Semester 2020] Device Programming

Language: VHDL - Size: 98.6 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

lucagrammer/Working-Zone

Final Project - Reti Logiche. Politecnico di Milano, A.A. 2019-2020

Language: VHDL - Size: 6.55 MB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

Bruno-Messias/EEL5105-Circuitos-e-Tecnicas-Digitais 📦

Material sobre projetos das aulas de CTD

Language: VHDL - Size: 3.1 MB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

HenryRocha/computer-design-mips-clock

MIPS DLX project for Insper's 2020.2 Computer Design class.

Language: VHDL - Size: 658 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 2

pratikbhuran/Up_Counter

VHDL implementation of Up counter.

Language: VHDL - Size: 13.7 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

DanielSouzaBertoldi/vhdl

Este projeto foi feito para a disciplina de Laboratório de Arquitetura de Computadores, e tem como objetivo implementar um MIPS simplificado utilizando-se da linguagem VHDL. As instruções implementadas para o microprocessador são: ADD, ADDI, SUB, LW, SW, BEQ, BNE, JAL, J, SLT, AND, OR, JR, SLL, SRL

Language: VHDL - Size: 5.28 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 1

jjwfisher/Ising-Spin-Sim 📦

Code for the Ising spin simulation

Language: VHDL - Size: 17.6 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

Liza23/Summer-of-Science_Automata-Theory

This repository contains the code written for implementation of digital circuits and is for the reading project on Automata theory under Summer of Science, conducted by Math & Physics Club, IIT Bombay.

Language: TeX - Size: 1.61 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

Stavros/4bitCounterParLoad

A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder

Language: VHDL - Size: 3.11 MB - Last synced at: 8 months ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

santosfilho/RISC-V-RV32I

Projeto de microprocessador utilizando o conjunto de instruções RV32I

Language: VHDL - Size: 4.65 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

Bsingstad/FYS4220_2019_lab1

UiO, FYS4220, Lab 1, 2019

Language: VHDL - Size: 5.94 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

MatheusAndrade1/Digital-Clock-in-VHDL

Digital clock in VHDL, on Altera Cyclone IV FPGA Board A-C4E6. This work was presented on PLP discipline during electrical engineer course at Mackenzie Presbyterian University.

Language: VHDL - Size: 1.28 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

LukeKan/fpga-manhattan-distance

FPGA design project for the course "Reti Logiche" of Politecnico di Milano, a.y. 2018/2019

Language: VHDL - Size: 293 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

torland-klev/INF3430-Projects 📦

Language: VHDL - Size: 51 MB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

Bsingstad/FYS4220_2019_lab2

UiO, FYS4220, Lab 2, 2019

Language: VHDL - Size: 1.51 MB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

ckevar/IIR-Filter

IIR Filter for audio application

Language: VHDL - Size: 10.7 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 4

motcodes/VHDL-Code-Beispiele

HTBLuVA Salzburg VHDL code examples for Finals

Size: 4.38 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

asl0007/DSD-VHDL-

PROGRAMS OF VHDL

Language: VHDL - Size: 2.26 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

nicobidone/Arquitectura_de_computadoras_I-FCExa-UNICEN

Trabajo práctico especial. Materia: Arquitectura de computadoras I. Año: 2017. UNICEN.

Language: VHDL - Size: 3.57 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

yishnu96/Number-Of-Once

VHDL PROGRAM

Language: HTML - Size: 109 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

JCLArriaga5/Bidirectional-SIPO_VHDL

Arquitectura de un registro de desplazamiento bidireccional SIPO

Language: VHDL - Size: 1000 Bytes - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

JCLArriaga5/8-bit-counter_VHDL

Arquitectura en VHDL de un contador de 8 bits

Language: VHDL - Size: 1000 Bytes - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

HuzaifaElahi/Space-Invaders

Language: VHDL - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

LFMP/CDII

Language: VHDL - Size: 58.9 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1

Ayush9719/Cache-Simulation-in-VHDL

This consists of a simulation of direct mapping in cache using VHDL

Language: VHDL - Size: 661 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

gitbritt/Computer_Architecture

Language: VHDL - Size: 294 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

alpteko/BlackJack-Game-for-FPGA

Language: VHDL - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1

pedrovivaldi/washing_machine

Washing machine program using VHDL

Language: VHDL - Size: 5 MB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 0

gurumanie-singh/gurumanie-singh.github.io

Unified GitHub Pages portfolio showcasing my Linux Bandit write-ups, Python networking tools, and coursework from COMS309, CPRE381, CPRE430, and COMS415.

Language: Python - Size: 145 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

EliasDeHondt/ExercisesIndustrialEngineerUniversityAntwerp

Collection of lab exercises (prácticas) and code from various courses in the Industrial Engineer: Electronics-ICT program at the University of Antwerp. Organized by subject with VHDL and C++ as examples.

Language: C++ - Size: 14.1 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

FahedWaheed8/Tracking-Room-Occupancy

Developing a reliable VHDL-based system to accurately track room occupancy in real time for smart building and security applications.

Language: VHDL - Size: 1.18 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0

njaalsb/VHDL

Kode i VHDL for utviklingskort DE-10, med FPGA Altera MAX 10M50DAF484C7G.

Language: VHDL - Size: 11.7 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

Korobonshi/VHDL_ROMLESS_DDFS

This repository contains the VHDL implementation of a ROM-less Direct Digital Frequency Synthesizer (DDFS) designed for high-speed calculation of the arctan function. This project was developed as a final assignment to fulfill the requirements for a bachelor's degree in my Electrical Engineering.

Language: VHDL - Size: 29.6 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

kostasnikolos/Logic-Gates-Designs

Logic & Digital Designs — VHDL — (Course: Logic Design / Digital Circuits, Semester X): small combinational and sequential VHDL designs (adders, encoders, counters, FSMs) with testbenches and waveforms, plus report.

Language: VHDL - Size: 255 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

Holandsoest/FPGA_I2C

WIP: An I2C-master AXI-slave, and I2C-Slave. So I can practice myself a bit, and build my own libraries.

Language: VHDL - Size: 313 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

CTipton27/FPGA_Pong

Language: VHDL - Size: 1.62 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

ElecGeek/MultiSignalGene

Generates multi channels sounds from primitives

Language: C++ - Size: 355 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: VHDL - Size: 184 KB - Last synced at: 2 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

SohamDas2004/RTL-Bundle

Important Verilog codes for both combinational and sequential circuits. Look into and explore!

Language: Verilog - Size: 0 Bytes - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

asazeez/COE608

COE608 Computer Organization and Architecture labs.

Language: VHDL - Size: 47 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

dannyvanderpol/nexys_a7_projects

Projects for the Nexys A7 FPGA development board

Language: Tcl - Size: 4.01 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

MateiB20/Proiect-n-echip-electronic-digital-

Counter– Registru Paralel

Language: Tcl - Size: 796 KB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

HMarchiori/relogio-xadrez-vhdl

Este projeto implementa um relógio de xadrez utilizando a linguagem VHDL. O sistema gerencia o tempo de jogo de dois jogadores e exibe os tempos restantes em um display.

Language: Tcl - Size: 8.79 KB - Last synced at: 4 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

DigitalDesignDen/open-scope-vhdl

Official repo of the open scope (a digital oscilloscope) developed by Digital Design Den

Language: VHDL - Size: 623 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Nyfeu/VHDL

This repository contains VHDL code and testbenches using GHDL, GTKWave, and Makefile.

Language: VHDL - Size: 91.8 KB - Last synced at: 5 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/32-bit-processor-with-vhdl Fork of ZIKOAR/32-bit-processor-with-vhdl

Forked from ZIKOAR's 32-bit-processor-with-vhdl repository.

Language: VHDL - Size: 6.84 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

VuxLoc/Digital_Design_With_VHDL

In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.

Size: 1000 Bytes - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0