GitHub / Florin623 1 repository

• Repositories 1
• Sort

  • Recently Pushed
  • Stars
  • Forks

Florin623/AXI-Lite-Slave-FPU-IP

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Language: VHDL - Size: 142 MB - Last synced: about 1 month ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

Florin623/AXI-Lite-Slave-FFT-IP

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

Language: VHDL - Size: 71.2 MB - Last synced: about 1 month ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

Florin623/Bash-Script-for-a-Calculator

A bash script for a calculator that performs addition, subtraction, multiplication, division and rise of power with floating point numbers. It also performs factorial.

Language: Shell - Size: 2.93 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/Blackjack-Game

Console-based Blackjack game in C++, allowing users to check cards, shuffle cards and play games

Language: C++ - Size: 15.6 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/Intelligent-Trash-Can

An intelligent trash can made using Arduino that detects motion around him, automatic opens the lid and signals when it is fully filled and must be emptied. An infrared sensor is used for motion detection, a stepper motor for lifting the lid and an ultrasonic sensor for fully filled detection.

Language: C++ - Size: 7.94 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/City-Management-System

Console-based city management system in C++, allowing users to add and remove buildings and people

Language: C++ - Size: 15.6 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/16-bit-RISC-Pipeline-Processor

4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.

Language: SystemVerilog - Size: 282 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/UART-Receiver

An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.

Language: SystemVerilog - Size: 4.74 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0