GitHub / Florin623 / AXI-Lite-Slave-FFT-IP

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Florin623%2FAXI-Lite-Slave-FFT-IP

Topics: axi, c-programming, communication-protocol, design, digital, electronics, fft, hardware, integrated-circuits, intellectual-property, interconnect, master-slave, microblaze, microelectronics, pipeline, processor, signal-processing, verilog, vitis, vivado

Files

No dependencies found