Xilinx/XRT

Run Time for AIE and FPGA based platforms

Language: C++ - Size: 111 MB - Last synced: 1 day ago - Pushed: 2 days ago - Stars: 513 - Forks: 449

efetunca/Zynq-7000-TFTP-Server

A TFTP server running on Zynq-7000

Language: C - Size: 3.83 MB - Last synced: about 10 hours ago - Pushed: 2 days ago - Stars: 0 - Forks: 0

t-kuha/kv260

Xilinx Kria KV260 Vision AI Starter Kit

Language: C - Size: 1.07 MB - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 0 - Forks: 1

Xilinx/Vitis-Tutorials

Vitis In-Depth Tutorials

Language: C - Size: 648 MB - Last synced: 10 days ago - Pushed: 10 days ago - Stars: 1,069 - Forks: 534

jmduarte/HLS_hls4ml_Tutorial

HLS & hls4ml Tutorial

Language: Jupyter Notebook - Size: 16.9 MB - Last synced: 6 days ago - Pushed: almost 4 years ago - Stars: 5 - Forks: 3

Xilinx/xup_vitis_network_example

VNx: Vitis Network Examples

Language: Jupyter Notebook - Size: 2.34 MB - Last synced: 20 days ago - Pushed: 20 days ago - Stars: 124 - Forks: 41

Florin623/AXI-Lite-Slave-FPU-IP

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Language: VHDL - Size: 142 MB - Last synced: 24 days ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/AXI-Lite-Slave-FFT-IP

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

Language: VHDL - Size: 71.2 MB - Last synced: 24 days ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

definelicht/hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Language: C++ - Size: 577 KB - Last synced: 24 days ago - Pushed: 24 days ago - Stars: 287 - Forks: 52

fpgasystems/Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

Language: C++ - Size: 2.17 MB - Last synced: 24 days ago - Pushed: 24 days ago - Stars: 160 - Forks: 68

FedericoSerafini/HLS-CNN

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

Language: C - Size: 21.6 MB - Last synced: 27 days ago - Pushed: 27 days ago - Stars: 22 - Forks: 5

Xilinx/Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

Language: C++ - Size: 249 MB - Last synced: about 19 hours ago - Pushed: 2 days ago - Stars: 62 - Forks: 23

JuantAldea/vitis_docker Fork of delafthi/vivado2022.1_docker

Docker container containing the Vitis 2023.2 tools & PetaLinux

Language: Dockerfile - Size: 3.33 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

spcl/apfp

FPGA acceleration of arbitrary precision floating point computations.

Language: C++ - Size: 304 KB - Last synced: 19 days ago - Pushed: about 2 years ago - Stars: 32 - Forks: 4

wakatime/tcl-prompt

Tcl plugin for powerlevel10k style prompt and WakaTime time tracking

Language: Tcl - Size: 49.8 KB - Last synced: about 1 month ago - Pushed: 5 months ago - Stars: 2 - Forks: 1

lvgl/lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

Language: C - Size: 82 MB - Last synced: 15 days ago - Pushed: 7 months ago - Stars: 14 - Forks: 4

Spyros-Papanastasiou-667/Z-turn-Board-V2-Diary

A newbie's diary on Zynq 🌌

Language: C++ - Size: 11.7 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

pavel-demin/red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

Language: Tcl - Size: 10.9 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 309 - Forks: 196

vacagonzalo/soc-workflow-firmware

Example workflow project for firmware development in Vitis.

Language: C - Size: 318 KB - Last synced: 2 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

pavel-demin/usb104-a7-notes

Notes on the USB104 A7 development board

Language: Tcl - Size: 1.11 MB - Last synced: 2 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

rogermiranda1000/Vivado_PS-PL_data_exchange

Creating a Custom IP for PS-PL data exchange in Vivado

Language: VHDL - Size: 5.32 MB - Last synced: 16 days ago - Pushed: 7 months ago - Stars: 4 - Forks: 0

CGCL-codes/ScalaBFS

A Scalable BFS Accelerator on FPGA-HBM Platform

Language: Scala - Size: 125 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 9 - Forks: 2

dsa-shua/FPGA-SystolicArray

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

Language: SystemVerilog - Size: 1.59 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

t-kuha/vai

Xilinx Vitis AI with custom models

Language: Jupyter Notebook - Size: 70.9 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 2 - Forks: 1

KasraAhmadi/window_method_error_detection

Error detection enabled Window method scalar multiplication on Elliptic Curves

Language: C++ - Size: 9.77 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

Xilinx/Vitis_Accel_Examples

Vitis_Accel_Examples

Language: Makefile - Size: 45.8 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 448 - Forks: 194

der-mur/zynq-freertos-sandbox

This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.

Language: C - Size: 32.8 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

lizardll/ScalaBFS

A Scalable BFS Accelerator on FPGA-HBM Platform

Language: Scala - Size: 67.9 MB - Last synced: 4 months ago - Pushed: almost 3 years ago - Stars: 13 - Forks: 2

Bassam-Kobasy/Vitis-IDE

This repo explain how to setup and install Vitis IDE for acceleration projects

Size: 32.2 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 2 - Forks: 1

noecochetel/North_American_Vitis_Pangenome

Construct and Analyze the North American Vitis pangenome

Language: R - Size: 328 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 12 - Forks: 3

pavel-demin/eclypse-z7-notes

Notes on the Eclypse Z7 development board

Language: C - Size: 387 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 9 - Forks: 2

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 1 - Forks: 0

miya4649/Vitis_KV260_KR260_Template

An bare metal application project template for Vitis unified IDE to start development easily (Support for AMD (Xilinx) Kria KV260, KR260)

Language: Tcl - Size: 8.79 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

esantosjr/FPGA-Function-Acceleration

Accelerating a simple function using an IP Block in the FPGA.

Language: Tcl - Size: 2.13 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

wyattduber/CyDAQ

CyDAQ DSP Platform Firmware and Software Redesign - Iowa State University Senior Design May 2023 Group 47 - Blake Fisher, Cole Langner, Corbin Kems, Jens Rasmussen, Long Zeng, Wyatt Duberstein, Yohan Bopearatchy

Language: C - Size: 984 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 2 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 2 - Forks: 1

t-kuha/ultra96-unified

Ultra96 (v1 & v2) projects

Language: C - Size: 61.6 MB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 2 - Forks: 1

Freed-Wu/xilinx-language-server

language server and vim plugin for xilinx vivado and vitis

Language: Vim Script - Size: 1.08 MB - Last synced: 2 days ago - Pushed: 4 days ago - Stars: 0 - Forks: 0

AnyDSL/flower

A Comprehensive Dataflow Compiler for High-Level Synthesis

Language: CMake - Size: 3.54 MB - Last synced: 9 months ago - Pushed: about 2 years ago - Stars: 5 - Forks: 1

michealcarac/SeniorCapstone

A Hardware-based Keylogging User Authentication System using a Zybo Z7 or Raspberry Pi

Language: VHDL - Size: 539 MB - Last synced: 9 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

cteqeu/SoC

Github Repo for Embedded FPGA course by Vincent Claes

Language: VHDL - Size: 518 MB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 7 - Forks: 13

cteqeu/PynqZ2

Size: 1.95 KB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0

Xilinx/xup_compute_acceleration

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

Language: C++ - Size: 20.2 MB - Last synced: 9 months ago - Pushed: 11 months ago - Stars: 42 - Forks: 13

tinaba96/master

Optimized-FDanQ: Implementation of Hybrid Neural Network "DanQ" on Cloud Multi-FPGA and its Optimization under Given Costs / Low-Complexity Quantization of decoding using Viterbi Algorithm

Language: VHDL - Size: 176 MB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 1 - Forks: 0

autohdw/flames

Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)

Language: C++ - Size: 485 KB - Last synced: 19 days ago - Pushed: 3 months ago - Stars: 2 - Forks: 0

vishalcseiitg/CS-577-C-BASED-VLSI-DESIGN

Course taken by Dr Chandan Karfa of Dept. of CSE, IIT Guwahati.

Language: C++ - Size: 71.2 MB - Last synced: 12 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

ribesstefano/Mapping-Multiple-LSTM-Models-on-FPGAs

Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.

Language: Jupyter Notebook - Size: 8.55 MB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 4 - Forks: 0

salehjg/DeepPoint-V2-FPGA

The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs

Language: C++ - Size: 361 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 3 - Forks: 2

ChienKaiMa/2021_ACA_HLS_team05

High level synthesis projects and practices

Language: C++ - Size: 54.7 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 3 - Forks: 0

extra2000/vitis-helloworld-linux 📦

Helloworld with Vitis on Linux

Language: Tcl - Size: 27.3 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

Lombiq/Hastlayer-Hardware-Framework---Vitis

Hardware-side component of Hastlayer for Xilinx Vitis FPGAs. See https://hastlayer.com for details.

Language: SystemVerilog - Size: 6.84 MB - Last synced: 19 days ago - Pushed: 4 months ago - Stars: 2 - Forks: 2

t-kuha/ultra96-v2-vitis 📦

Ultra96 (v2) projects for Vitis platform

Language: Tcl - Size: 7.29 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 1 - Forks: 0

t-kuha/ultra96-vitis 📦

Ultra96 (v1) projects for Vitis platform

Language: C - Size: 10.1 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 2 - Forks: 1

JoseAmador95/UoS_RSoC 📦

Reconfigurable Systems on Chip Mini Project

Language: VHDL - Size: 53.2 MB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 2 - Forks: 1

yyboom/2021_project_Pacman

[2021-1][기초디지털실험] Final project

Language: VHDL - Size: 37.5 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

jasonlin316/GCN-Inference-Acceleration-HLS

An end-to-end GCN inference accelerator written in HLS

Language: C++ - Size: 390 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 9 - Forks: 2

extra2000/vitis-ledxor 📦

LEDXOR with Vitis (C++14) and EMIO GPIO

Language: Tcl - Size: 40 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 0 - Forks: 0

extra2000/vitis-cpp-datastruct 📦

C++ Data Structure with Vitis

Language: Tcl - Size: 142 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

extra2000/vitis-gpio-led 📦

MIO GPIO programming with C++14

Language: Tcl - Size: 29.3 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 0 - Forks: 0

ihsanalhafiz/SVM_Speech_Recognition-Vitis_IDE

Language: C - Size: 8.86 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

jlscheerer/matrix-profile-hls

Systolic array-based Matrix Profile Computation implemented in Vitis™ HLS for Xilinx FPGAs.

Language: C++ - Size: 35.9 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 1 - Forks: 0

catarinaacsilva/md5-hardware

System based on hardware (FPGA) and software to implement MD5 Cryptographic Hash Function

Language: VHDL - Size: 286 MB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 0

kaanolgu/matrix_multiplications

Vitis 2020.1 Acceleration Examples and Developed Large Size Matrix Multiplication Examples

Language: C++ - Size: 567 KB - Last synced: 11 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 1

sgherbst/jtag_test

Fully-automated Vivado + SDK example that tests an emulated JTAG TAP controller

Language: C - Size: 91.8 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 3 - Forks: 0

beetleboxorg/Getting-started-with-BeetleboxCI-and-Vitis-Running-FAST

Learn how to get started with BeetleboxCI and Vitis Unified Development Environment with this tutorial covering using computer vision on FPGA technology

Language: C++ - Size: 2.29 MB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 1 - Forks: 0

riccardonicolaidis/PmodSD_Arty_A7_Project

In this project I wanted to implement a microprocessor on an FPGA with the ability to write files onto an SD card (micro SD in particular) exploiting the Arty A7 development board and the Digilent PModSD.

Language: VHDL - Size: 144 MB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 1

Juanx65/Aguilera_Mardones_T4_3_2_IPD432

T4 P3.2 - Procesador de vectores implementado en ZYBO

Language: VHDL - Size: 3.68 MB - Last synced: 11 months ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

Juanx65/Aguilera_Mardones_T4_3_1_IPD432

Tarea 4 Parte 3.1 IPD432 - Procesador de vectores para Nexys4 DDR

Language: VHDL - Size: 87 MB - Last synced: 11 months ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

brnaguiar/cr-16bit-lfsr

Implementation of a (soft) coprocessor for the computation of a 16 bit LFSR.

Language: VHDL - Size: 43.8 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 1

cothan/Vitis_High_Level_Synthesis_Training

Vitis High Level Synthesis Introduction

Language: C++ - Size: 4.37 MB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 1 - Forks: 1

extra2000/vitis-helloworld-baremetal

Helloworld with Vitis on bare metal (standalone single-core)

Language: Tcl - Size: 32.2 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

riccardonicolaidis/project_getting_started_Vivado_Vitis

Personal revision of the tutorial "Getting started with Vivado and Vitis for Baremetal system" by Digilent.

Language: VHDL - Size: 87.8 MB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

ros-acceleration/vitis_common

Common code for working with Vitis™ Unified Software Platform in ROS 2.

Language: C++ - Size: 539 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 5

Steinegger/vivado-lxc

Launch an Ubuntu lxc container and install Xilinx Vitis/Vivado

Language: Shell - Size: 23.4 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 2

BabarZKhan/tapasco_counter_versions

Language: C++ - Size: 8.79 KB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 0 - Forks: 0

KeitetsuWorks/Vitis-Platform-Ultra96-V2-v2020.1

Ultra96-V2 Vitis Platform for Xilinx Design Tools version 2020.1

Language: C - Size: 6.04 MB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 1 - Forks: 0

trash4299/RSDecoderSW

Vince's Vitis workspace for RSDecoder. Platform, system, and application for the RSDecoder hardware

Language: C - Size: 9.24 MB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0