VLSI-Shubh/Morphological-Image-Filtering-on-PYNQ-FPGA

Morphological image filtering system on PYNQ-Z2 FPGA implementing min, max, and median filters. Demonstrates HW/SW co-design with VHDL acceleration and Python orchestration for real-time image enhancement

Language: VHDL - Size: 1.39 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Language: C - Size: 24.5 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 4,320 - Forks: 725

bsc-pm-ompss-at-fpga/ait

The Accelerator Integration Tool (AIT) automatically integrates OmpSs@FPGA accelerators into FPGA designs using different vendor backends

Language: Tcl - Size: 10.5 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 6 - Forks: 2

Dpbm/faculdade

Meus programas que fiz durante o curso de ciencias da computacao

Language: Jupyter Notebook - Size: 27.5 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 1 - Forks: 0

Thraetaona/Innervator

Innervator: Hardware Acceleration for Neural Networks

Language: VHDL - Size: 2.86 MB - Last synced at: 10 days ago - Pushed at: about 1 year ago - Stars: 17 - Forks: 2

f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Language: Jupyter Notebook - Size: 9.52 MB - Last synced at: 8 days ago - Pushed at: 12 days ago - Stars: 293 - Forks: 115

jmduarte/HLS_hls4ml_Tutorial

HLS & hls4ml Tutorial

Language: Jupyter Notebook - Size: 16.9 MB - Last synced at: 3 days ago - Pushed at: about 5 years ago - Stars: 13 - Forks: 6

conneroisu/cpre488-mp2

CPRE488 MP2 - 1080p HDMI video pipeline for Zynq using Vivado/Vitis—TPG→VDMA with GenLock→VTC→HDMI, plus YUV422 luminance processing and FMC I²C bring-up

Language: VHDL - Size: 930 MB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 1 - Forks: 0

mcleber/Bug_fixes_and_Configuration_Files

This repository compiles notes, fixes, and configuration files related to bugs and issues encountered during the installation and use of various software tools on both Linux and Windows platforms.

Size: 150 KB - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 0

f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

Language: Python - Size: 6.51 MB - Last synced at: 29 days ago - Pushed at: 3 months ago - Stars: 818 - Forks: 159

Ba1tu3han/PYNQ_Thesis

(3/3) Running (inference) the trained, quantized and compiled NN model in Xilinx PYNQ Z2 FPGA Board

Language: Jupyter Notebook - Size: 568 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

viktor-nikolov/ILI9488-Xilinx

ILI9488 TFT SPI display library for Xilinx SoC and FPGA

Language: C - Size: 60.8 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 9 - Forks: 1

SayantanMandal2000/electronic-voting-machine-verilog

🚀 RTL design and testbench implementation of a Digital Electronic Voting Machine (EVM) using Verilog HDL. The EVM is modeled with a modular, FSM-based architecture suitable for FPGA or ASIC prototyping and educational use.

Language: Verilog - Size: 1.84 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

tariqjamel/Image-Processing-in-Verilog

An image processing pipeline written in Verilog that performs RAW Bayer to RGB conversion and applies 3x3 convolution filters like blur and identity for pixel-level image enhancement.

Language: Verilog - Size: 62.5 KB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

f4pga/prjxray-db

Project X-Ray Database: XC7 Series

Language: Shell - Size: 62.5 MB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 70 - Forks: 36

ThuyPham/FPGA-Toturial

FPGA Tutorial Basic thuypx.com

Language: VHDL - Size: 16.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

stavrakas13/FIR-filter-for-FPGA-Zybo

As part of the laboratory exercise of Dig. VSLI in ECE NTUA, me and Ioannis Danias, we designed in VHDL, a FIR filter for the Zybo board which communicates with it via AXI LITE.

Language: VHDL - Size: 15.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

ingonyama-zk/open-binius

building blocks for accelerating ZK proofs over binary fields

Language: Verilog - Size: 9.61 MB - Last synced at: about 1 month ago - Pushed at: 3 months ago - Stars: 45 - Forks: 3

KUBUSrozwala/Matrix-Calculator

Solve 2×2 and 3×3 matrix operations step-by-step with our user-friendly app. Perfect for students and educators! 🐙📊

Language: Python - Size: 1.85 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

fredrequin/verilator_xilinx

Re-coded Xilinx primitives for Verilator use

Language: Verilog - Size: 155 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 49 - Forks: 5

Kampi/VHDL

Some VHDL projects, created with and for my ZYBO.

Language: VHDL - Size: 79.6 MB - Last synced at: 8 days ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

jofrfu/HAW-V

Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg

Language: VHDL - Size: 31.9 MB - Last synced at: 3 months ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 3

markus-k/rv32-soc

A simple RISC-V SoC based on picorv32

Language: VHDL - Size: 26.4 KB - Last synced at: 1 day ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0

ingonyama-zk/blaze

blaze is a Rust library for ZK acceleration on Xilinx FPGAs.

Language: Rust - Size: 2.25 MB - Last synced at: 10 days ago - Pushed at: 11 months ago - Stars: 144 - Forks: 18

nesterovmaxim31/Simpson-s-rule-Verilog

Построение синхронного цифрового автомата для реализации метода Симсона с дальнейшей загрузкой на ПЛИС Artix-7 xс7a100tcsg324-1I

Language: Verilog - Size: 1.36 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

aproposorg/KV260-PYNQ-tutorial

Simple PYNQ KV260 tutorial: Porting C-based design into FPGA via Xilinx HLS

Language: Jupyter Notebook - Size: 106 MB - Last synced at: 4 months ago - Pushed at: almost 2 years ago - Stars: 7 - Forks: 3

ashvnv/FPGA-Ping-Pong-game

Simple Ping Pong game on Xilinx Spartan 3E

Language: HTML - Size: 13.9 MB - Last synced at: 27 days ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 2

briansune/Kintex-7-MIPI-DSI-10.1-inch-LCD

Kintex 7 MIPI DSI 10.1" LCD

Size: 3.54 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

briansune/Kintex-7-MIPI-DSI-5.5-inch-LCD-C

Kintex 7 MIPI DSI 5.5" LCD Model-C

Size: 2.48 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

ayusdixit/Hardware_Codesign_lab

hardware software codesign Lab at IITJ

Language: C - Size: 21 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 1

triSYCL/sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

Language: C++ - Size: 1.37 GB - Last synced at: 4 months ago - Pushed at: 10 months ago - Stars: 118 - Forks: 21

Un2versidad/Digital-Logic

Introduction to VHDL and Digital Logic - Basys 3 and Vivado Projects Repository

Language: Tcl - Size: 2.02 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 1

JeffDeCola/control-fpga-via-raspi-and-webserver

Control a FPGA via a Raspberry Pi and a Webserver.

Language: JavaScript - Size: 16.4 MB - Last synced at: 13 days ago - Pushed at: 5 months ago - Stars: 4 - Forks: 0

geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

Language: Verilog - Size: 11.6 MB - Last synced at: 4 months ago - Pushed at: about 4 years ago - Stars: 25 - Forks: 4

EMATech/zynq_book_pynq-z1

Zynq Book Tutorials adapted for the Digilent PYNQ-Z1

Language: Tcl - Size: 6.84 KB - Last synced at: 4 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

derekmulcahy/xvcpi

Xilinx Virtual Cable Server for Raspberry Pi

Language: C - Size: 290 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 113 - Forks: 28

klimatt/arty_a7

A playground with various modules, written in SystemVerilog, with a project setup to simplify working routines.

Language: SystemVerilog - Size: 27.7 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

SeungjaeLim/Efficient-Road-Repairs-System

[KAIST CS632] Road damage detection using YOLOv8 on Xilinx FPGA, repair estimation with vLLM-Serve Phi-3.5 FAISS RAG, and data management via GS1 EPCISv2 and React dashboard

Language: Python - Size: 86.4 MB - Last synced at: 14 days ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

ultraembedded/core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

Language: C++ - Size: 4.29 MB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 94 - Forks: 27

Wissance/QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Language: Verilog - Size: 127 KB - Last synced at: 5 months ago - Pushed at: almost 8 years ago - Stars: 22 - Forks: 7

chipsalliance/yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Language: Verilog - Size: 4.57 MB - Last synced at: 29 days ago - Pushed at: over 1 year ago - Stars: 83 - Forks: 50

pourya-kgp/HBAonFPGA

Implementation of Hardware Bee Algorithm (HBA) on FPGA for solving the Traveling Salesperson Problem (TSP) (M.S. Thesis)

Language: MATLAB - Size: 25.5 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

cemkayhan/kv260_affine_transform_demo

4K 30 fps Affine Transform IP core implementation demo on Kria KV260 Vision AI Starter Kit

Size: 276 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Kampi/OV7670

FPGA interface and driver for an OV7670 camera sensor.

Language: VHDL - Size: 31.3 KB - Last synced at: 8 days ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 1

Slatyo/SonarTracking

Small project to track things with a waterproof sonar sensor

Language: C++ - Size: 2.22 MB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

ultraembedded/openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Language: Verilog - Size: 606 KB - Last synced at: 7 months ago - Pushed at: about 4 years ago - Stars: 133 - Forks: 18

charkster/spi_slave_verilog

SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs

Language: Verilog - Size: 30.3 KB - Last synced at: 6 months ago - Pushed at: over 5 years ago - Stars: 15 - Forks: 11

Wissance/ImageCaptureSystem

A Xilinx IP Core and App for line scanner image capture and store

Language: VHDL - Size: 43.6 MB - Last synced at: 5 months ago - Pushed at: about 8 years ago - Stars: 10 - Forks: 6

istiak8empire/Hands-on-Project-of-Verilog-HDL

Implementing Hands-on Project of Verilog-HDL

Language: Verilog - Size: 1.98 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Bubi2001/DaedaLogic

FPGA dev board based off AMD Xilinx Artix 7 XC7A35T-1FTG256C with lots of peripherals

Size: 3.91 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

ultraembedded/core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer

Language: Verilog - Size: 77.1 KB - Last synced at: 7 months ago - Pushed at: about 5 years ago - Stars: 79 - Forks: 12

gundasrikar/Sleepy-Keeper-FPGA-XILINX

Size: 1.95 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

InvincibleJuggernaut/ProgSqrWavGen

A programmable square wave generator developed with ZedBoard

Language: VHDL - Size: 46.1 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

10x-Engineers/Infinite-ISP_FPGABinaries

Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit and Efinix® Titanium Ti180 J484 Development Kit

Language: Python - Size: 52.4 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 6 - Forks: 4

SalvatoreBarone/CNN-VHDL

A library of VHDL components for Neural Networks

Language: C++ - Size: 32.8 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 17 - Forks: 3

Bucknalla/AD9361_ZyCAP

PL Layer Controls for the AD9361 RF Front End

Size: 747 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

saikamat/AEP Fork of sappyh/AEP

Advanced Embedded Systems Project: Image Topology Extraction

Language: VHDL - Size: 76 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

bsc-pm-ompss-at-fpga/ompss-2-at-fpga-releases

Meta-repository for OmpSs-2@FPGA releases

Language: Makefile - Size: 67.4 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

TheMightyDuckOfDoom/projectXCxk

Reverse-engineering of early Xilinx FPGAs

Language: Python - Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

AnyDSL/flower

A Comprehensive Dataflow Compiler for High-Level Synthesis

Language: CMake - Size: 3.68 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 9 - Forks: 4

sajadh76/UART-Protocol

Discover the Xilinx Spartan-6 FPGA implementation featuring a UART protocol and Bubble Sort algorithm

Language: VHDL - Size: 8.79 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 5 - Forks: 0

FrankKesel/xilinx_tools

Xilinx Tools Tutorials

Language: C++ - Size: 36.7 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

splAcharya/DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Size: 71.2 MB - Last synced at: 10 months ago - Pushed at: about 5 years ago - Stars: 18 - Forks: 4

shinesunnysom/Biofeedback-Game-System

CECS 490A/490B Course; Senior Project Design

Language: Verilog - Size: 742 KB - Last synced at: 6 months ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 0

mcedrdiego/Kria_yolov3_ppe

Xilinx Kria KV260 Real-time PPE detection

Language: C++ - Size: 116 MB - Last synced at: 5 months ago - Pushed at: over 2 years ago - Stars: 13 - Forks: 0

AndreasKaratzas/graphics-driver

Custom graphics driver using Verilog on Xilinx FPGA platform.

Language: Verilog - Size: 156 KB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 0

charkster/cmod_a7_spi_sram

SPI slave to External SRAM interface for Cmod A7

Language: SystemVerilog - Size: 13.7 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 1

adamchristiansen/vivado-scripts 📦

Keep Xilinx Vivado projects as minimal git repositories. A fork of https://github.com/Digilent/digilent-vivado-scripts

Language: Tcl - Size: 29.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1

gao-yiheng/Nexys3

Verilog code that could run on Nexys3 (Spartan-6)

Language: Verilog - Size: 60.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

luminoso/cr-countones

Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs

Language: VHDL - Size: 25.6 MB - Last synced at: 11 months ago - Pushed at: about 8 years ago - Stars: 7 - Forks: 1

hex-five/multizone-iot-sdk

MultiZone® Trusted Firmware is the quick and safe way to build secure IoT applications with any RISC-V processor. It provides secure access to commercial and private IoT clouds, real-time monitoring, secure boot, and remote firmware updates. The built-in Trusted Execution Environment provides hardware-enforced separation ...

Language: C - Size: 8.31 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 19 - Forks: 1

Prithvish04/reconfigurable_project

Canny edge detection in HLS

Language: Jupyter Notebook - Size: 10.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

mabowers/xc2064-clock

Desk clock based on the Xilinx XC2064 FPGA

Language: OCaml - Size: 116 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

islandcontroller/ArduinoXVC

Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo

Language: C++ - Size: 139 KB - Last synced at: 5 months ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 2

atmughrabi/GraphBlox

GraphBlox: A Vertex Centric Re-Configurable Graph Processing Overlay

Language: SystemVerilog - Size: 280 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

NicolaZomer/SoundWaveDistortionViaFPGA

Implementation on FPGA of a distortion effect in sound waves called "Overdrive" or "Clipping" as a final project of the couse Management and Analysis of Physics Dataset (mod.A).

Language: SystemVerilog - Size: 30.5 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 1

erihsu/TinySoC

Arm cortex-m3 based SoC implementation used for simple car plane recognization

Language: V - Size: 38.5 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

0xastro/RTL_QAM

The project is designed using VHDL to realise the M-QAM modulation.

Language: VHDL - Size: 13.6 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 1

sahilmgandhi/m152b-fall2018

CS M152B Codebase Fall 2018

Language: HTML - Size: 43.5 MB - Last synced at: 18 days ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 1

ArioKian/Xilinx_Zynq7000_PS_SLCR_RegistersDrivers

Zynq-7000 PS side drivers for SLCR Registers.

Language: C - Size: 6.84 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Elon-Wang/Breakout

Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.

Language: VHDL - Size: 29.7 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

f4pga/prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Language: SystemVerilog - Size: 1.37 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 66 - Forks: 12

sahmad98/HardwareDesigns

Few of my VHDL hardware design for Xilinx Spartan 6 board

Language: VHDL - Size: 10.7 KB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

ArioKian/Xilinx_Zynq7000_ZynqUltraScalePlus_PS_SdCardDrivers

Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.

Language: C - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-ArtyA7_Blinky

The code allows anyone with the Artix A7 FPGA Board to Blink the On-Board LED for any predefined Frequency.

Language: Tcl - Size: 32.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 21 - Forks: 2

siorpaes/SimpleSoC

Very simple Cortex-M1 SoC design based on ARM DesignStart

Language: C - Size: 206 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 8 - Forks: 2

onegentig/VUT-FIT-INC2022-projekt 📦

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

Language: VHDL - Size: 255 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

onegentig/VUT-FIT-IVH2023-projekt 📦

Projekt (animace na maticovém displeji) z předmětu Seminář VHDL (IVH), čtvrtý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Language: VHDL - Size: 420 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

DenizKrdy98/Scrolling-Text-on-FPGA-VHDL-Coding

VHDL project done on FPGA board as for Digital Design Course ELEC204. I implement a such code that can scroll the selected word on selected pace and direction using VHDL.

Size: 433 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

ViktorSlavkovic/FPGA_Tetris

FPGA Tetris written in Verilog

Language: Verilog - Size: 75.2 KB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 7 - Forks: 2

BabarZKhan/tapasco_counter_versions

Language: C++ - Size: 8.79 KB - Last synced at: 6 months ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

Bassam-Kobasy/Vitis-IDE

This repo explain how to setup and install Vitis IDE for acceleration projects

Size: 32.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

ngiambla/qvmi

Quick Verilog Module Isolator - Isolates a design for testing.

Language: Verilog - Size: 233 KB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 0

KorktheMighty/DC-motor-based-winch-system

[From class ELEN 242] Using Xlinix SDK and a Basys 3 board, joystick, motor, and LCD screen to simulate a DC motor winch with information being displayed on the LCD screen

Language: C - Size: 0 Bytes - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced at: 6 months ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

lazyoracle/vhdl-processor

An 8-bit processor in VHDL based on a simple instruction set

Language: VHDL - Size: 209 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 0

Kampi/TinyAVR

VHDL design of an AVR8 CPU.

Language: VHDL - Size: 1.63 MB - Last synced at: 8 days ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 0

santifs/ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

Language: VHDL - Size: 6.83 MB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 8 - Forks: 2

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 6 - Forks: 2