pConst/basic_verilog

Must-have verilog systemverilog modules

Language: Verilog - Size: 54.2 MB - Last synced: 3 days ago - Pushed: 3 days ago - Stars: 1,456 - Forks: 340

MJoergen/HyperRAM

Portable HyperRAM controller

Language: VHDL - Size: 3.31 MB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 44 - Forks: 9

otaviocmaciel/DAC-MCP482x-VHDL-core

MCP482x DAC Family VHDL Core

Language: VHDL - Size: 5.68 MB - Last synced: 9 days ago - Pushed: 9 days ago - Stars: 0 - Forks: 0

QuestIO42/vlab Fork of rafaelaroca/RemoteMicrocontrollerLab

A set of PHP files, scripts and database to allow remote users to edit programs, upload code and access the serial port of real microcontrollers.

Language: PHP - Size: 6.1 MB - Last synced: 9 days ago - Pushed: 10 days ago - Stars: 1 - Forks: 0

robseb/Django2FPGAdemo

Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework

Language: Python - Size: 2.38 MB - Last synced: 10 days ago - Pushed: almost 3 years ago - Stars: 11 - Forks: 4

robseb/rstoolsA10

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA

Language: C++ - Size: 1.27 MB - Last synced: 10 days ago - Pushed: almost 3 years ago - Stars: 5 - Forks: 2

robseb/HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Language: Verilog - Size: 11 MB - Last synced: 10 days ago - Pushed: almost 3 years ago - Stars: 34 - Forks: 12

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced: 11 days ago - Pushed: 4 months ago - Stars: 1,025 - Forks: 107

robseb/meta-intelfpga

Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide

Language: BitBake - Size: 589 KB - Last synced: 10 days ago - Pushed: 12 days ago - Stars: 20 - Forks: 6

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1010 KB - Last synced: 13 days ago - Pushed: 14 days ago - Stars: 596 - Forks: 180

har-in-air/FPGA_STEREO_CROSSOVER

Stereo digital 2-way crossover filters processing I2S audio (16bit or 24bit) streams

Language: C++ - Size: 4.44 MB - Last synced: 18 days ago - Pushed: 18 days ago - Stars: 14 - Forks: 1

drandyhaas/Haasoscope

Docs, design, firmware, and software for the Haasoscope

Language: Verilog - Size: 81.6 MB - Last synced: 20 days ago - Pushed: 20 days ago - Stars: 108 - Forks: 37

f32c/f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Language: C - Size: 11.2 MB - Last synced: 20 days ago - Pushed: 20 days ago - Stars: 395 - Forks: 110

hukenovs/fp32_logic

Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.

Language: VHDL - Size: 26.4 KB - Last synced: 12 days ago - Pushed: over 5 years ago - Stars: 7 - Forks: 2

nmarcopo/alteraMetronome

A metronome created with an Altera DE2-115 board and the hardware description language Verilog.

Language: Verilog - Size: 5.74 MB - Last synced: 27 days ago - Pushed: almost 6 years ago - Stars: 0 - Forks: 0

nmarcopo/alteraLaser

A variant on the classic "Breakout" video game, but the ball cuts through the bricks - like a laser!

Language: Verilog - Size: 10 MB - Last synced: 27 days ago - Pushed: almost 6 years ago - Stars: 1 - Forks: 0

proboterror/ZX_BUS_Mouse

ZX BUS Kempston Mouse Controller

Language: C - Size: 5.19 MB - Last synced: 27 days ago - Pushed: 28 days ago - Stars: 2 - Forks: 0

jesusjimsa/Desarrollo-de-Hardware-Digital-UGR

Prácticas de la asignatura de Desarrollo de Hardware Digital en la UGR

Language: VHDL - Size: 41.1 MB - Last synced: 29 days ago - Pushed: about 5 years ago - Stars: 0 - Forks: 0

tilk/sextium-iii-verilog

Sextium® III processor implemented in Verilog

Language: Verilog - Size: 226 KB - Last synced: 29 days ago - Pushed: almost 6 years ago - Stars: 3 - Forks: 0

montao/nios2-mmu

Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.

Language: Verilog - Size: 31.3 MB - Last synced: 30 days ago - Pushed: about 7 years ago - Stars: 2 - Forks: 2

MKme/fpga

FPGA and CPLD programming, tutorials and information I figure out.

Language: VHDL - Size: 4.37 MB - Last synced: 30 days ago - Pushed: over 2 years ago - Stars: 1 - Forks: 0

iDoka/awesome-fpga-boards

:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................

Size: 9.28 MB - Last synced: 8 days ago - Pushed: over 3 years ago - Stars: 84 - Forks: 11

PyFPGA/pyfpga

A Python package to use FPGA development tools programmatically.

Language: Python - Size: 4.38 MB - Last synced: about 10 hours ago - Pushed: 1 day ago - Stars: 77 - Forks: 7

thomask77/ct-ng-toolchains

Bare-Metal ARM Toolchains for Altera SoCFPGA and NXP LPC32xx targets

Language: Shell - Size: 15.6 KB - Last synced: about 1 month ago - Pushed: almost 6 years ago - Stars: 3 - Forks: 3

ua1arn/hftrx

Embedded firmware for ham radio transceivers

Language: C - Size: 759 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 69 - Forks: 30

Charlie-Ramirez-Animation-Studios-de-MX/VHDL-Basicos

Programas Basicos en Lenguaje VHDL de Diseño Logico y Diseño de Circuitos Digitales para Uso y simulacion con QuartusII y los FPGA Cyclone III de Altera (Compilados y compatibles con la FPGA EP3C16F484C6N) Para Practica en la Licenciatura de Ingenieria Electrica Electronica e Ingenieria en Computación Bajo Licencia MIT

Language: VHDL - Size: 20.5 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

ljishen/altera-fpga-demos

Language: C++ - Size: 36 MB - Last synced: about 1 month ago - Pushed: almost 7 years ago - Stars: 0 - Forks: 0

hukenovs/fp23fftk

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

Language: VHDL - Size: 1.27 MB - Last synced: 12 days ago - Pushed: almost 2 years ago - Stars: 48 - Forks: 15

hukenovs/intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

Language: VHDL - Size: 309 KB - Last synced: 12 days ago - Pushed: over 1 year ago - Stars: 71 - Forks: 25

halfmanhalftaco/fpga-docker

Tools for running FPGA vendor toolchains with Docker

Language: Makefile - Size: 32.2 KB - Last synced: 26 days ago - Pushed: about 1 year ago - Stars: 66 - Forks: 14

jairov4/puj-ca-de1-audio-pump

Base files for project in Computer Architecture course of 2014-2

Language: C - Size: 1.68 MB - Last synced: about 1 month ago - Pushed: about 9 years ago - Stars: 1 - Forks: 0

leonow32/verilog-fpga

Many peripherals in Verilog ready to use

Language: Verilog - Size: 4.89 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 22 - Forks: 3

obiwanjacobi/Zalt

Zalt is a home brew Z80 computer with a modern(isch) chipset.

Language: C - Size: 94.2 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 14 - Forks: 3

OpenFPGAduino/fpga

The fpga project for openFPGAdunino

Language: Verilog - Size: 377 KB - Last synced: about 1 month ago - Pushed: over 6 years ago - Stars: 6 - Forks: 4

hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Language: VHDL - Size: 1.82 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 36 - Forks: 1

tomverbeure/intel_jtag_uart

A Python module to interact with an Intel JTAG UART

Language: Python - Size: 147 KB - Last synced: about 1 month ago - Pushed: about 3 years ago - Stars: 17 - Forks: 2

BrianHGinc/BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Language: SystemVerilog - Size: 9.94 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 64 - Forks: 28

jagumiel/Data-Acquisition

This repository contains some examples of data acquisition over MATLAB, LabVIEW and VHDL.

Language: C - Size: 399 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 2 - Forks: 0

nobotro/fpga_riscv_cpu

fpga verilog risc-v rv32i cpu

Language: Verilog - Size: 97.3 MB - Last synced: 14 days ago - Pushed: about 1 year ago - Stars: 8 - Forks: 2

OpenFPGAduino/OpenFPGAduino

All open source file and project for OpenFPGAduino project

Language: Makefile - Size: 151 KB - Last synced: about 1 month ago - Pushed: over 5 years ago - Stars: 156 - Forks: 28

arnaldojr/Robot-FPGA

Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.

Language: VHDL - Size: 25.4 KB - Last synced: 2 months ago - Pushed: over 4 years ago - Stars: 2 - Forks: 0

VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Language: VHDL - Size: 4.96 MB - Last synced: about 2 months ago - Pushed: over 3 years ago - Stars: 511 - Forks: 95

michaelmortensen-m4y/Michael_RISC-V_Chisel

RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA

Language: Scala - Size: 3.03 MB - Last synced: 3 months ago - Pushed: over 6 years ago - Stars: 1 - Forks: 0

yuleeque/fpga_altera_cyclone_3

FPGA peripherals

Language: VHDL - Size: 181 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 3 - Forks: 0

iDoka/GOST-28147-89

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

Language: Verilog - Size: 34.2 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 12 - Forks: 2

zenek65/Quartus-HEX-16bit

convert avr 8bit intel HEX to Altera 16 bit HEX format

Language: Pascal - Size: 5.61 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

qubeck78/RiscVSOCQ13

RiscV based SOC with 2D and 3D graphics acceleration ( Altera Cyclone IV GX ) and some software examples

Language: VHDL - Size: 34.2 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

akaeba/mifgen

MIF convertor

Language: Python - Size: 28.3 KB - Last synced: about 2 months ago - Pushed: 5 months ago - Stars: 1 - Forks: 0

MJoergen/Avalon

Utilities for Avalon Memory Map

Language: VHDL - Size: 977 KB - Last synced: 2 months ago - Pushed: 4 months ago - Stars: 5 - Forks: 0

pedro-javierf/AlteraDE1pinfiles

Pin file in .qsf format for Altera DE1 FPGA

Language: Tcl - Size: 5.46 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 1 - Forks: 0

mshr-h/fibonacci_verilog

fibonacci number calculator written in Verilog-HDL

Language: Verilog - Size: 41 KB - Last synced: 29 days ago - Pushed: over 7 years ago - Stars: 3 - Forks: 0

smirnovich/nios_ii_basics

NIOS II® lab resources for a course

Language: C - Size: 5.19 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

SpPap/Shift_Register

My implementation of CD54HC194 shift register.

Language: VHDL - Size: 976 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

rezapace/Golang-Altera

berisikan tugas dan materi pada kampusmerdeka (100% - Mastering Golang Programming) "Repo Go-muhammad-reza-hidayat (rezapace) - proyek Go dengan dokumentasi baik, dukungan Docker."

Language: Go - Size: 155 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 1

rezapace/Presencee-BE Fork of Capstone-Alta-18/Presencee-BE

"Repository backend Go Presencee-BE, CI/CD AWS, struktur clean architecture."

Language: Go - Size: 26.3 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

rezapace/miniprojek

miniprojek altera golang "Repo "miniprojek" oleh rezapace: Backend Go untuk manajemen kafe. Struktur terorganisir, dukungan Docker, dokumentasi lengkap, dan skema database SQL."

Language: Go - Size: 7.85 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

ryanvickr/Taillight-Control-Unit

An automobile taillight control unit I created using VHDL, programmed to run on the Altera Cyclone V board.

Language: VHDL - Size: 17.6 KB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0

mithro/ixo-usb-jtag Fork of svn2github/ixo-usb-jtag

usb-jtag - Altera USB Blaster Emulation with a FX2

Language: C++ - Size: 181 KB - Last synced: about 2 months ago - Pushed: almost 3 years ago - Stars: 66 - Forks: 30

kiclu/arp

RISC-V based microprocessor system for Altera DE0 FPGA board

Language: VHDL - Size: 56.6 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 5 - Forks: 0

delhatch/Pure_Mandel

FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.

Language: Verilog - Size: 38.7 MB - Last synced: 7 months ago - Pushed: over 6 years ago - Stars: 6 - Forks: 1

delhatch/Flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

Language: Verilog - Size: 18.8 MB - Last synced: 7 months ago - Pushed: about 6 years ago - Stars: 1 - Forks: 1

voldemoriarty/Matmul

Matrix Multiplication in Hardware

Language: C - Size: 40.7 MB - Last synced: 7 months ago - Pushed: almost 4 years ago - Stars: 9 - Forks: 3

MohammedRashad/FPGA-Speech-Recognition

Expiremental Speech Recognition System using VHDL & MATLAB.

Language: VHDL - Size: 37.1 KB - Last synced: 7 months ago - Pushed: about 6 years ago - Stars: 38 - Forks: 18

yasaspeiris/VHDL-LiftSimulator

A finite state machine in VHDL modeled after an elevator

Language: VHDL - Size: 8.71 MB - Last synced: 7 months ago - Pushed: almost 5 years ago - Stars: 0 - Forks: 1

hukenovs/adc_configurator

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

Language: VHDL - Size: 17.6 KB - Last synced: 12 days ago - Pushed: almost 6 years ago - Stars: 11 - Forks: 0

ZygalM1S1U/Altera-OpenCL-Toolset-for-Intel-FPGA-SDK

This program is to assist as a toolset for OpenCl's FPGA SDK. Since the OpenCL has a certain standard and procedure of compiling and transferring mehods to the board, this tool set was written to assist in plain english.

Language: C - Size: 57.6 KB - Last synced: 7 months ago - Pushed: about 6 years ago - Stars: 3 - Forks: 0

delhatch/Spectrum

Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

Language: VHDL - Size: 37.9 MB - Last synced: 7 months ago - Pushed: over 6 years ago - Stars: 24 - Forks: 10

thinkoco/c5soc_opencl

DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

Language: Verilog - Size: 30.5 MB - Last synced: 7 months ago - Pushed: over 3 years ago - Stars: 84 - Forks: 39

jonpalmisc/usb_blaster_arm64

Altera USB Blaster drivers for Windows 11 Arm

Language: Shell - Size: 6.84 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 1 - Forks: 1

AlexLevitin/VHDL_Encryptor_Decryptor

Encryption/Decryption unit in FPGA written in VHDL with use of test benches and simulations

Size: 14.5 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

Mat5heus/Whatspaper-Web

É uma extensão para navegadores chromium que altera o papel de parede do Whatsapp web

Language: JavaScript - Size: 1.27 MB - Last synced: 8 months ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

GSimas/EEL7123

🖩Repositório para Disciplina EEL7123 - Tópico Avançado em Sistemas Digitais - UFSC

Language: VHDL - Size: 73.3 MB - Last synced: about 2 months ago - Pushed: over 4 years ago - Stars: 2 - Forks: 0

lstolcman/vga_controller

Language: Verilog - Size: 2.48 MB - Last synced: 9 months ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0

lstolcman/bachelor-thesis

Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract

Language: Verilog - Size: 228 MB - Last synced: 9 months ago - Pushed: about 6 years ago - Stars: 4 - Forks: 1

feddischson/de0_led_example

A very small example project for the Terasic DE0 SOC board.

Language: Makefile - Size: 4.88 KB - Last synced: 10 months ago - Pushed: over 5 years ago - Stars: 1 - Forks: 3

feddischson/de0_hps_example

Examples for the Terasic DE0-nano-SOC board

Language: Makefile - Size: 51.8 KB - Last synced: 10 months ago - Pushed: about 6 years ago - Stars: 1 - Forks: 0

MarianDubei/PingPongFPGA

Ping Pong game on an FPGA in Verilog using HDMI

Language: Verilog - Size: 22.1 MB - Last synced: 10 months ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 1

nikolovjovan/FPGAParallelSorting 📦

Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.

Language: VHDL - Size: 1.97 MB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 2 - Forks: 0

rauhul/ece385

Digital Systems Laboratory UIUC FA 2016

Language: Verilog - Size: 55.5 MB - Last synced: 10 months ago - Pushed: over 7 years ago - Stars: 1 - Forks: 0

macmata/buildroot Fork of buildroot/buildroot

Personal modification

Language: Makefile - Size: 69.6 MB - Last synced: 10 months ago - Pushed: over 5 years ago - Stars: 0 - Forks: 1

amaranth-farm/fpga-mandelbrot

FPGA mandelbrot accelerator via high speed/super speed USB

Language: Python - Size: 119 KB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 11 - Forks: 4

yerminal/TicTacToe

This is an METU-EE314 Term Project named TicTacToe (game) implemented on DE1-Soc board.

Language: Tcl - Size: 283 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

Paebbels/pyIPCMI

A Python-based IP Core Management Infrastructure.

Language: Python - Size: 578 KB - Last synced: 8 days ago - Pushed: about 3 years ago - Stars: 8 - Forks: 6

trozodejamon/ep4ce6CoreBoard

A basic set of resources to help you get started with the commonly available and cheap AliExpress Altera Cyclone IV EP4CE6E22C8 FPGA Core Boards. No warranty expressed or implied.

Size: 2.38 MB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 0 - Forks: 0

delhatch/Red_Tracker

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

Language: Verilog - Size: 14.5 MB - Last synced: 7 months ago - Pushed: over 6 years ago - Stars: 11 - Forks: 2

Bryce-Leung/FPGA-UART-Protocol

UART Protocol made for Altera DE2-115 FPGA in VHDL

Language: VHDL - Size: 46.9 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 1

aileneiioana/NiosII_HDL

Language: Verilog - Size: 215 MB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 0 - Forks: 0

AndryMaullana/prakerja_final_projek

Final Projek untuk unjuk keterampilan di course prakerja altera academy

Language: Go - Size: 27.3 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

b-dmitry1/V188

FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)

Language: Verilog - Size: 2.26 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 6 - Forks: 1

dilshan/max2-audio-dac

24-bit Stereo Audio DAC for Raspberry Pi

Language: Verilog - Size: 366 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 26 - Forks: 7

robseb/rstoolsCY5

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA

Language: C - Size: 1.74 MB - Last synced: 10 days ago - Pushed: 5 months ago - Stars: 4 - Forks: 4

wyvernSemi/lm32fpga

FPGA development board (DE1) targetted lm32 based systems design for Verilog

Language: Python - Size: 5.42 MB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 2 - Forks: 0

BrianHGinc/SystemVerilog-HDMI-encoder-serializer-PLL-generator

SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.

Language: SystemVerilog - Size: 91.8 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 7 - Forks: 1

tocache/Altera-Cyclone-II-FPGA

Repositorio de proyectos hechos en el Quartus II para el FPGA Cyclone II

Language: C - Size: 229 MB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 5 - Forks: 1

aingthawan/VHDL_Nbit_Calculator

VHDL programming about basic N-bit binary calculator ( + - x / ) for altera fpga cyclone v board

Language: VHDL - Size: 13.7 KB - Last synced: 12 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

stpe/jniosemu

JNiosEmu is an educational Nios II based development environment and emulator with the purpose of making it easy to learn programming in assembler. Assemble your source with a single button click, immediately see how values change in a register or memory. All this without any prior knowledge of assembler programming or complex tool chains.

Language: Java - Size: 1.07 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 8 - Forks: 9

panda5mt/KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Language: Scala - Size: 19.6 MB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 39 - Forks: 3

iDoka/mastering-fpgasic-book

:book: Mastering FPGASIC Book

Size: 1.95 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 14 - Forks: 4

fjpolo/CourseraFPGADesignforEmbeddedSystemsSpecialization

Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-

Language: Verilog - Size: 94.3 MB - Last synced: over 1 year ago - Pushed: about 3 years ago - Stars: 8 - Forks: 3

suoto/vim-hdl 📦

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

Language: Python - Size: 460 KB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 61 - Forks: 6