GitHub / hdl-modules / hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-modules%2Fhdl-modules
Stars: 169
Forks: 29
Open issues: 9
License: bsd-3-clause
Language: VHDL
Size: 3.47 MB
Dependencies parsed at: Pending
Created at: over 1 year ago
Updated at: 5 days ago
Pushed at: 4 days ago
Last synced at: 4 days ago
Commit Stats
Commits: 414
Authors: 4
Mean commits per author: 103.5
Development Distribution Score: 0.42
More commit stats: https://commits.ecosyste.ms/hosts/GitHub/repositories/hdl-modules/hdl-modules
Topics: altera, amd, asic, asynchronous-fifo, axi, axi-lite, cdc, clock-domain-crossing, eda, efinix, fifo, fpga, hardware, intel, ip, microsemi, rtl, vhdl, vivado, xilinx