volkanbenzer/Basic_UART

This project was created for easy communication between your FPGA and other devices includes UART interface like PC, MCU etc. The code was tested on Spartan 3E FPGA dev. board

Language: C - Size: 1.17 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

soni3006/basic_logic_gates_with_verilog

basic logic gates are implemented using verilog languege and simulation is done in xilinx vivado

Language: JavaScript - Size: 75.2 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

Elihelmo/Kintex-7-MIPI-DSI-6.9-inch-LCD

This repository contains a Verilog-based HDL design for driving a 6.9-inch MIPI DSI LCD using the Kintex-7 FPGA. Explore the project to simplify your display initialization without relying on complex IPs. 🖥️🌟

Size: 2.14 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

brown9804/NexysDDR4-RISC-V_picorv32

Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU

Language: Verilog - Size: 85 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 2 - Forks: 3

pavel-demin/red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

Language: Tcl - Size: 11.1 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 362 - Forks: 218

Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Language: VHDL - Size: 25 MB - Last synced at: 1 day ago - Pushed at: 14 days ago - Stars: 200 - Forks: 39

quentinprieels/rfnoc-ofdm

An RFNoC OOT module for implementing an OFDM receiver on USRP devices, as part of my master thesis.

Language: Python - Size: 1.05 GB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 4 - Forks: 0

briansune/Artix-Kintex-7-MIPI-DSI-4.5-inch-LCD

Artix or Kintex 7 MIPI DSI 4.5" LCD

Size: 5.78 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

AlvaroDavi5/Programacao_e_Desenvolvimento

Language: JavaScript - Size: 306 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

cong2738/May_team_project_I2C_SPI

i2c com, spi com with AMBA AXI

Language: VHDL - Size: 71.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 3

akhil-b-26/parametric-low-power-alu

A configurable Arithmetic Logic Unit (ALU) supporting 12 operations with parameterized data width. Designed with low-power techniques including clock gating and operand isolation. Simulated using Xilinx Vivado WebPACK with waveform verification.

Language: Verilog - Size: 35.2 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.24 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 324 - Forks: 81

briansune/Kintex-7-MIPI-DSI-5-inch-LCD

Size: 6.65 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0

JPShag/PCILeech-DMA-Firmware

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

Language: C - Size: 35.4 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 285 - Forks: 78

nesterovmaxim31/Simpson-s-rule-Verilog

Построение синхронного цифрового автомата для реализации метода Симсона с дальнейшей загрузкой на ПЛИС Artix-7 xс7a100tcsg324-1I

Language: Verilog - Size: 1.36 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

briansune/Kintex-7-MIPI-DSI-6.9-inch-LCD

Size: 0 Bytes - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

PyFPGA/pyfpga

A Python package to use FPGA development tools programmatically.

Language: Python - Size: 7.15 MB - Last synced at: 6 days ago - Pushed at: 2 months ago - Stars: 134 - Forks: 15

Subbu-kata/SSIT

This project implements a smart, contactless water dispensing system using FPGA technology. Designed for hygiene-critical environments, the system uses infrared (IR) proximity sensors to detect hand presence and activates a centrifigual pump for flow of water accordingly—eliminating the need for physical contact.

Language: Verilog - Size: 15.6 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.24 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 25 - Forks: 5

yomnahisham/ts-verilog-simulator

A web-based Verilog simulator for designing, running, and visualizing RTL code in-browser. Built with Next.js 14, TypeScript, Tailwind CSS, and Monaco Editor on the frontend, and FastAPI with a custom Python simulation engine on the backend with real-time simulation, interactive waveform viewing, multi-file support, and automated module detection.

Language: TypeScript - Size: 300 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 5 - Forks: 0

Xilinx/RapidWright

Build Customized FPGA Implementations for Vivado

Language: Java - Size: 7.59 MB - Last synced at: 6 days ago - Pushed at: 7 days ago - Stars: 320 - Forks: 116

themperek/cocotb-vivado

Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

Language: Python - Size: 36.1 KB - Last synced at: 3 days ago - Pushed at: 4 months ago - Stars: 43 - Forks: 8

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced at: 9 days ago - Pushed at: over 1 year ago - Stars: 1,159 - Forks: 127

konosubakonoakua/vivtool

vivado utilities

Language: Python - Size: 0 Bytes - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

somnath503/verilog-vending-machine

A Verilog HDL-based vending machine project using FSM and simulated in Xilinx Vivado.

Language: Verilog - Size: 134 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 1 - Forks: 0

miranda1000/Vivado_PS-PL_data_exchange

Creating a Custom IP for PS-PL data exchange in Vivado

Language: VHDL - Size: 5.32 MB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 0

Sped0n/eko

BSc Thesis: Design of Sound Source Localization System Based on FPGA and MEMS Microphone.

Language: VHDL - Size: 311 MB - Last synced at: 5 days ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0

MJoergen/HyperRAM

Portable HyperRAM controller

Language: VHDL - Size: 4.2 MB - Last synced at: 6 days ago - Pushed at: 6 months ago - Stars: 55 - Forks: 14

jofrfu/tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Language: VHDL - Size: 1.42 MB - Last synced at: 8 days ago - Pushed at: over 6 years ago - Stars: 465 - Forks: 66

mwrnd/innova2_flex_xcku15p_notes

Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development

Language: Tcl - Size: 39.5 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 60 - Forks: 8

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.08 MB - Last synced at: 13 days ago - Pushed at: 29 days ago - Stars: 687 - Forks: 201

pavel-demin/giga-zee-notes

Notes on the GigaZee modules

Language: C - Size: 299 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 4 - Forks: 0

dannyvanderpol/nexys_a7_projects

Projects for the Nexys A7 FPGA development board

Language: Tcl - Size: 4.01 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 0 - Forks: 0

fastmachinelearning/hls4ml

Machine learning on FPGAs using HLS

Language: C++ - Size: 257 MB - Last synced at: 13 days ago - Pushed at: 28 days ago - Stars: 1,477 - Forks: 454

uio33/Kintex-7-MIPI-DSI-5.5-inch-4K-LCD

Kintex 7 MIPI DSI 5.5" 4K LCD

Size: 2.64 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0

hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Language: VHDL - Size: 3.63 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 165 - Forks: 29

jorgeloopzz/Practicas-HP

Prácticas de laboratorio de la asignatura Hardware Programable

Language: Tcl - Size: 1.66 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 1 - Forks: 0

MatthieuMichon/vivado-vhdl-time-const-calc

Xilinx Vivado issue with VHDL time type handling

Language: Tcl - Size: 0 Bytes - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0

changwoolee/lenet5_hls

FPGA Accelerator for CNN using Vivado HLS

Language: C++ - Size: 105 MB - Last synced at: 15 days ago - Pushed at: over 3 years ago - Stars: 316 - Forks: 92

riskci/Artix-Kintex-7-MIPI-DSI-4.5-inch-LCD

The Artix-Kintex-7-MIPI-DSI-4.5-inch-LCD is a compact display module designed for embedded systems, featuring high-resolution visuals and low power consumption. It supports MIPI DSI interface, making it ideal for applications in mobile devices and portable electronics.

Size: 5.17 MB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

briansune/Kintex-7-MIPI-DSI-10.1-inch-LCD

Kintex 7 MIPI DSI 10.1" LCD

Size: 3.54 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 0 - Forks: 0

AliQorbaniFard/basic_logic_gates_with_verilog

basic logic gates are implemented using verilog languege and simulation is done in xilinx vivado

Language: JavaScript - Size: 0 Bytes - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 1 - Forks: 0

briansune/Kintex-7-MIPI-DSI-5.5-inch-LCD-C

Kintex 7 MIPI DSI 5.5" LCD Model-C

Size: 2.48 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 0 - Forks: 0

Kampi/VHDL

Some VHDL projects, created with and for my ZYBO.

Language: VHDL - Size: 79.6 MB - Last synced at: 1 day ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

briansune/Kintex-7-MIPI-DSI-5.5-inch-4K-LCD

Kintex 7 MIPI DSI 5.5" 4K LCD

Size: 2.64 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 1 - Forks: 0

PalouJaume/OsciBoard 📦

This archive documents the development of a Wien Bridge Oscillator designed to generate a 10 kHz sinusoidal signal.

Language: VHDL - Size: 56.4 MB - Last synced at: 19 days ago - Pushed at: 28 days ago - Stars: 1 - Forks: 0

edaa-org/pyEDAA.ToolSetup

Language: Python - Size: 5.36 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 5 - Forks: 0

ItzzInfinity/100-days-of-RTL

Trying to get a new skill

Language: Verilog - Size: 79.5 MB - Last synced at: 21 days ago - Pushed at: 5 months ago - Stars: 23 - Forks: 6

briansune/Artix-Kintex-7-MIPI-DSI-3.97-inch-LCD

Artix & Kintex 7 MIPI DSI 3.97 inch LCD

Size: 4.08 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

demianmozo/sound_detector_NN

This project was developed as the final work for the course "From Algorithm to Hardware: Machine Learning in Embedded Systems".

Language: Ada - Size: 358 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

tomas-fryza/vhdl-labs

VHDL course at Brno University of Technology

Language: Tcl - Size: 47.1 MB - Last synced at: 13 days ago - Pushed at: about 1 month ago - Stars: 110 - Forks: 230

RDSik/axis-i2c-master

AXI-Stream I2C Master module

Language: SystemVerilog - Size: 275 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

yunusesergun/yesergun.fpga.dev

All about FPGA...

Language: Tcl - Size: 2.24 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

Un2versidad/Digital-Logic

Introduction to VHDL and Digital Logic - Basys 3 and Vivado Projects Repository

Language: Tcl - Size: 2.02 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 1

alpyen/fpga-mediaplayer

HDL, Hardware & Software Development project to playback a video with sound and learn while doing so.

Language: VHDL - Size: 13.2 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Language: Tcl - Size: 36.1 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 933 - Forks: 209

hpcn-uam/Limago 📦

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

Language: Tcl - Size: 1.17 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 125 - Forks: 47

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.7 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 36 - Forks: 11

f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

Language: Python - Size: 6.51 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 796 - Forks: 156

ashtacore/NexysA7Scratch

This is me playing around with my Nexys A7 and learning verilog. This is the Vivado project directory.

Language: Tcl - Size: 952 KB - Last synced at: 3 days ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

dan-lara/Spectrum-Analyzer

This project aims to develop a spectrum analyzer system using the Zynq-7000 board. The system will capture audio input (I2S), process it through a well-defined internal architecture, and output the data via DMA to a VGA screen. The VGA screen will display the signal as a frequency spectrum using FFT (Fast Fourier Transform).

Language: C - Size: 2.56 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

LaErre9/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102

Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.

Language: Jupyter Notebook - Size: 252 MB - Last synced at: 4 days ago - Pushed at: about 1 year ago - Stars: 16 - Forks: 2

dau-dev/vivado-docker

Minimal Dockerized Vivado

Language: Shell - Size: 5.86 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

IamMosiow/SPI-Master-VHDL

FSM-based SPI Master implementation in VHDL with simulation and docs

Language: VHDL - Size: 271 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Amalkrishnan-P/FPGA_Based_Fault_Analyser_for_Industrial_Motors

Simple hardware accelerator for fft computation

Language: Jupyter Notebook - Size: 2.93 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Language: SystemVerilog - Size: 820 KB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 275 - Forks: 60

weisrc/nesv

NESystem Verilog

Language: SystemVerilog - Size: 1.11 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

tuna-sahin/Bilkent-EEE102-Labs

My VHDL files for the lab assignments for EEE102 Digital Systems Design

Language: VHDL - Size: 30.4 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

Language: Verilog - Size: 2.03 MB - Last synced at: 12 days ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

chipsalliance/f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

Language: Verilog - Size: 1.34 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 13 - Forks: 13

vgalovic/HDL_examples

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.

Language: VHDL - Size: 182 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 4 - Forks: 0

Freed-Wu/xilinx-language-server

language server and vim plugin for xilinx vivado and vitis

Language: Vim Script - Size: 1.08 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 4 - Forks: 0

b00rg/32-bit-processor

Simulating a 32-bit processor using VHDL

Language: VHDL - Size: 10.5 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

bsilente/Intelligent-Parking-Lot-Management-System-Based-on-FPGA

基于FPGA的智能停车场车牌识别与管理系统是面向广大智能停车场开发的一款产品，采用先进的车牌定位、字符分割与识别算法，结合FPGA硬件加速，实现对车辆出入停车场的实时、准确车牌识别。 此外，该系统还集成了车位检测、自动计费、反向寻车等功能，提供全方位的停车场智能化管理。同时，本系统使用模块化设计，融合了升降杆的自动控制系统，提升用户停车体验。 本作品利用FPGA的高速并行处理能力，实现一套高效、智能的停车场车牌识别与管理系统，解决传统停车场管理效率低、人工成本高、用户体验差等问题，为智慧城市建设贡献力量。

Language: VHDL - Size: 227 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 4 - Forks: 0

patrickleboutillier/jcscpu-hw

Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

Language: Verilog - Size: 268 KB - Last synced at: about 2 months ago - Pushed at: almost 5 years ago - Stars: 15 - Forks: 3

glazzarelli/progetto-reti-logice-2021

Progetto Finale di Reti Logiche.

Language: VHDL - Size: 417 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

sifferman/fusesoc_template

Example of how to get started with olofk/fusesoc.

Language: Python - Size: 10.7 KB - Last synced at: 10 days ago - Pushed at: almost 4 years ago - Stars: 17 - Forks: 0

yokeTH/vivado-mac

Language: Shell - Size: 1.23 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 2 - Forks: 2

hyeokls/fpga_timer

FPGA 타이머 제작

Language: VHDL - Size: 0 Bytes - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

Teddy-van-Jerry/sdr-psk-fpga

Dual-Mode PSK Transceiver on SDR With FPGA

Language: Verilog - Size: 281 MB - Last synced at: 2 months ago - Pushed at: 8 months ago - Stars: 28 - Forks: 13

cas-mls/cpu2

This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date.

Language: VHDL - Size: 363 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Beckversync/RISC_CPU_Beckham

A SystemVerilog implementation of a simple FPGA memory module is presented, featuring a single bidirectional data port. The design is accompanied by a testbench for thorough functional verification.

Language: JavaScript - Size: 1.31 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 2 - Forks: 0

MOLATERS/Vivado-project

哈尔滨工业大学 计算机体系结构 五级流水线处理器

Language: VHDL - Size: 92.7 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

whatever125/schoolRISCV Fork of zhelnio/schoolRISCV

Лабораторная работа «Расширение возможностей учебного процессорного ядра schoolRISCV» по курсу «Функциональная схемотехника», ИТМО ИВТ 3 курс 2024

Language: Makefile - Size: 15.3 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

continuum5531/RISC-V

This project features a 32-bit accumulator-based processor designed following the Von Neumann architecture, optimized for efficient computation. It implements a 16-opcode instruction set with multiple addressing modes, ensuring flexibility in instruction execution and data manipulation.

Language: Verilog - Size: 20.5 KB - Last synced at: 17 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

yuanbo-peng/Combination-Lock

This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.

Language: VHDL - Size: 1020 KB - Last synced at: 5 days ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 3

li3tuo4/rc-fpga-zcu

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

Language: Tcl - Size: 79.9 MB - Last synced at: about 1 month ago - Pushed at: about 2 years ago - Stars: 61 - Forks: 17

tymonx/pytcl

Mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 25.4 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

Layheng-Hok/Digital-Piano

Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100

Language: Verilog - Size: 9.97 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 1

lvgl/lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

Language: C - Size: 82 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 22 - Forks: 5

cemkayhan/kv260_affine_transform_demo

4K 30 fps Affine Transform IP core implementation demo on Kria KV260 Vision AI Starter Kit

Size: 276 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

cemkayhan/affine_transform

4K 30fps capable Affine Transform IP core implementation

Language: C++ - Size: 0 Bytes - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

MatteoFasulo/Versal-C-Code

Evaluation of timing performance of deep neural networks workloads accelerated on Versal AI Engine in presence of contention on shared resources, mainly caused by ARM Cortex A72 dual-core microprocessor.

Language: Jupyter Notebook - Size: 4.43 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

FabioAccurso/ASDi

Collection of exercises done during the course “Digital Systems Architectures” in my master's degree program in computer engineering.

Language: Tcl - Size: 30.3 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

TahirZia-1/RISC-V-CPU-Core-SystemVerilog

This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.

Language: SystemVerilog - Size: 11.9 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Spyros667/Z-turn-Board-V2-Diary

A newbie's diary on Zynq 🌌

Language: HTML - Size: 12.2 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

TahirZia-1/UART-Transmitter-and-Receiver

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

TahirZia-1/Digital-Clock-Verilog

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Language: Tcl - Size: 166 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

qubeck78/tangerineA7_100

RISC-V based SOC for Qmtech Artix7-100 Wukong board with 720p VGA, DDR3 and cache controller

Language: VHDL - Size: 2.21 GB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0