GitHub | Ecosyste.ms: Repos

Prajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

Language: Tcl - Size: 146 KB - Last synced: about 5 hours ago - Pushed: over 1 year ago - Stars: 4 - Forks: 1

tomas-fryza/vhdl-course

VHDL course at Brno University of Technology

Language: Tcl - Size: 46.1 MB - Last synced: about 17 hours ago - Pushed: about 17 hours ago - Stars: 77 - Forks: 230

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.17 MB - Last synced: 1 day ago - Pushed: 2 days ago - Stars: 7 - Forks: 1

f4pga/prjxray

Documenting the Xilinx 7-series bit-stream format.

Language: Python - Size: 6.4 MB - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 739 - Forks: 148

HDLGen-ChatGPT/PYNQ-SoC-Builder

This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

Language: Python - Size: 18.6 MB - Last synced: 8 days ago - Pushed: 8 days ago - Stars: 1 - Forks: 1

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1000 KB - Last synced: 8 days ago - Pushed: 9 days ago - Stars: 593 - Forks: 179

WangXuan95/Zynq-Tutorial

使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例

Language: C - Size: 49.4 MB - Last synced: 4 days ago - Pushed: 8 months ago - Stars: 75 - Forks: 12

MJoergen/HyperRAM

Portable HyperRAM controller

Language: VHDL - Size: 3.31 MB - Last synced: 9 days ago - Pushed: 10 days ago - Stars: 44 - Forks: 8

Shuregg/FPGA-practicum

learning about FPGA

Language: Tcl - Size: 1.24 MB - Last synced: 10 days ago - Pushed: 11 days ago - Stars: 0 - Forks: 0

eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Language: Tcl - Size: 35.4 MB - Last synced: 10 days ago - Pushed: 10 days ago - Stars: 741 - Forks: 173

digital-design-snu/ANPPV_RISC_PipelinedProcessor

Language: Verilog - Size: 3.75 MB - Last synced: 11 days ago - Pushed: about 7 years ago - Stars: 5 - Forks: 0

cpantel/prog_fpgas

The nexys4ddr (vivado) port of https://github.com/simonmonk/prog_fpgas (ISE)

Language: Verilog - Size: 98.6 KB - Last synced: 11 days ago - Pushed: over 4 years ago - Stars: 1 - Forks: 1

Xilinx/RapidWright

Build Customized FPGA Implementations for Vivado

Language: Java - Size: 7.07 MB - Last synced: 12 days ago - Pushed: 13 days ago - Stars: 271 - Forks: 101

muhammadtalhasami/Axi4_lite_interface

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

Language: SystemVerilog - Size: 104 KB - Last synced: 12 days ago - Pushed: 13 days ago - Stars: 0 - Forks: 1

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.13 MB - Last synced: 15 days ago - Pushed: 17 days ago - Stars: 277 - Forks: 76

RDSik/i2c_master

Language: Verilog - Size: 38.1 KB - Last synced: 13 days ago - Pushed: 13 days ago - Stars: 0 - Forks: 0

AlvaroDavi5/Programacao_e_Desenvolvimento

Language: JavaScript - Size: 306 MB - Last synced: 14 days ago - Pushed: 15 days ago - Stars: 0 - Forks: 0

raleighlittles/Applied_Digital_Logic_Exercises_Using_FPGAs

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

Language: Verilog - Size: 13.2 MB - Last synced: 15 days ago - Pushed: over 2 years ago - Stars: 8 - Forks: 1

recolic/vivado-wrapper

This is a read-only mirror for https://git.recolic.net/root/vivado-wrapper

Language: Shell - Size: 85 KB - Last synced: 15 days ago - Pushed: about 3 years ago - Stars: 12 - Forks: 2

jmduarte/HLS_hls4ml_Tutorial

HLS & hls4ml Tutorial

Language: Jupyter Notebook - Size: 16.9 MB - Last synced: 5 days ago - Pushed: almost 4 years ago - Stars: 5 - Forks: 3

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced: 15 days ago - Pushed: 3 months ago - Stars: 1,011 - Forks: 105

princeranjan03/ImageEncryption_I-CHIP

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

Language: Verilog - Size: 7.3 MB - Last synced: 20 days ago - Pushed: 20 days ago - Stars: 0 - Forks: 0

MarcoBendinelli/VHDL-Histogram-Equalization-Module

VHDL module for histogram equalization, aiming to enhance image contrast using digital circuit design techniques in VHDL

Language: VHDL - Size: 4.25 MB - Last synced: 21 days ago - Pushed: 21 days ago - Stars: 0 - Forks: 0

Florin623/AXI-Lite-Slave-FPU-IP

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Language: VHDL - Size: 142 MB - Last synced: 23 days ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/AXI-Lite-Slave-FFT-IP

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

Language: VHDL - Size: 71.2 MB - Last synced: 23 days ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

Florin623/16-bit-RISC-Pipeline-Processor

4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.

Language: SystemVerilog - Size: 282 KB - Last synced: 23 days ago - Pushed: 23 days ago - Stars: 0 - Forks: 0

Florin623/UART-Receiver

An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.

Language: SystemVerilog - Size: 4.74 MB - Last synced: 23 days ago - Pushed: 23 days ago - Stars: 0 - Forks: 0

gio-del/Progetto-Reti-Logiche-2021-22

Language: VHDL - Size: 970 KB - Last synced: 23 days ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

Language: Verilog - Size: 37.8 MB - Last synced: 25 days ago - Pushed: 25 days ago - Stars: 17 - Forks: 0

mvsoliveira/PCBpy

A Cadence Allegro PCB schematics parser and verification tool. Together with IBERTpy can configure, run, and compile Vivado IBERT eye diagrams using information from Cadence Allegro schematics.

Language: Python - Size: 9.51 MB - Last synced: 13 days ago - Pushed: about 3 years ago - Stars: 14 - Forks: 5

iBug/Nexys4-DDR-stopwatch 📦

A stopwatch on Digilent Nexys4 DDR written in Verilog

Language: VHDL - Size: 2.47 MB - Last synced: 29 days ago - Pushed: over 5 years ago - Stars: 1 - Forks: 0

RiccardoSagramoni/convolutional-code-generator 📦

University Project for "Electronics and Communication Systems" course (MSc Computer Engineering @ University of Pisa). VHDL design and logical synthesis of a convolutional code generator.

Language: VHDL - Size: 2.14 MB - Last synced: 29 days ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

yunpengn/EE2020

EE2020 Digital Fundamentals @ NUS Engin

Language: Verilog - Size: 20 MB - Last synced: about 1 month ago - Pushed: over 6 years ago - Stars: 0 - Forks: 0

hedhyw/simple-4bit-cpu

Vivado project with example of simple 4bit CPU

Language: Verilog - Size: 671 KB - Last synced: about 1 month ago - Pushed: about 5 years ago - Stars: 2 - Forks: 0

qubeck78/tangerineSOCMA7

tangyRiscVSOC - Mimas A7 port

Language: VHDL - Size: 25 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

fastmachinelearning/hls4ml

Machine learning on FPGAs using HLS

Language: C++ - Size: 251 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1,086 - Forks: 379

RDSik/FPGA-transceiver

Language: Verilog - Size: 400 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Language: VHDL - Size: 1.82 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 36 - Forks: 1

yasanthaniroshan/NanoProcessor

A Nanoprocessor designed to run on the Basys3 FPGA desgined using Xlinx Vivado with VHD using Registers, Add/Sub Unit, Decoders, Multiplexers which have been implemented seperately.

Language: JavaScript - Size: 7.2 MB - Last synced: 29 days ago - Pushed: 3 months ago - Stars: 1 - Forks: 1

calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

Language: Verilog - Size: 920 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

zslwyuan/Hi-ClockFlow

Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

Size: 7.81 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1 - Forks: 0

kamplianitis/SingleCycleProcessor

Single cycle processor Design for the purposes of the course Computer Organisation at Technical University of Crete (TUC)

Language: VHDL - Size: 261 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 2 - Forks: 2

OpenPixelSystems/go-vivado-tcl-generator

Tool to easily generate TCL scripts for a vivado build using a generic template

Language: Go - Size: 8.79 KB - Last synced: about 1 month ago - Pushed: over 4 years ago - Stars: 0 - Forks: 0

Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Language: VHDL - Size: 25 MB - Last synced: about 1 month ago - Pushed: 8 months ago - Stars: 155 - Forks: 35

JuantAldea/vitis_docker Fork of delafthi/vivado2022.1_docker

Docker container containing the Vitis 2023.2 tools & PetaLinux

Language: Dockerfile - Size: 3.33 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

LaErre9/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102

Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.

Language: Jupyter Notebook - Size: 252 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 9 - Forks: 1

arhamhashmi01/sv-practice

This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language

Language: SystemVerilog - Size: 6.84 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

JalalSayed1/N-bit-Multiplier

N-bit Multiplier implementation in VHDL

Language: VHDL - Size: 3.3 MB - Last synced: about 1 month ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

JalalSayed1/N-bit-Full-Adder

N-bit Full Adders implementation in VHDL

Language: Tcl - Size: 19.1 MB - Last synced: about 1 month ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

HDLGen-ChatGPT/HDLGen-ChatGPT

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Language: Python - Size: 125 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 11 - Forks: 9

R4sp1/digital-electronics-1-project

Team project in BPC-DE1 course on FEEC BUT

Language: VHDL - Size: 77.8 MB - Last synced: about 1 month ago - Pushed: about 2 years ago - Stars: 0 - Forks: 1

wakatime/tcl-prompt

Tcl plugin for powerlevel10k style prompt and WakaTime time tracking

Language: Tcl - Size: 49.8 KB - Last synced: about 1 month ago - Pushed: 5 months ago - Stars: 2 - Forks: 1

Mihiro1ll1/PmodSTEP-Controller

PmodSTEP Controller IP Package for Vivado

Language: Tcl - Size: 20.5 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

LeiWang1999/FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Size: 58.6 KB - Last synced: about 2 months ago - Pushed: about 2 years ago - Stars: 3,249 - Forks: 593

lvgl/lv_port_xilinx_zedboard_vitis

This repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals

Language: C - Size: 82 MB - Last synced: 15 days ago - Pushed: 7 months ago - Stars: 14 - Forks: 4

mwrnd/innova2_flex_xcku15p_notes

Nvidia/Mellanox Innova-2 Flex Open Programmable SmartNIC Setup and Usage Notes for XCKU15P FPGA Development

Language: Tcl - Size: 39.2 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 34 - Forks: 6

Spyros-Papanastasiou-667/Z-turn-Board-V2-Diary

A newbie's diary on Zynq 🌌

Language: C++ - Size: 11.7 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

Elon-Wang/Breakout

Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.

Language: VHDL - Size: 29.7 MB - Last synced: 19 days ago - Pushed: almost 5 years ago - Stars: 2 - Forks: 0

hpcn-uam/Limago 📦

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

Language: Tcl - Size: 1.17 MB - Last synced: about 2 months ago - Pushed: over 2 years ago - Stars: 109 - Forks: 45

ntuifranklin/ENES-246

Language: JavaScript - Size: 3.52 MB - Last synced: about 2 months ago - Pushed: about 5 years ago - Stars: 0 - Forks: 0

f4pga/prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Language: SystemVerilog - Size: 1.37 MB - Last synced: about 1 month ago - Pushed: over 2 years ago - Stars: 66 - Forks: 12

pavel-demin/red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

Language: Tcl - Size: 10.9 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 309 - Forks: 196

sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Language: SystemVerilog - Size: 253 KB - Last synced: 25 days ago - Pushed: over 3 years ago - Stars: 41 - Forks: 5

Abdelrahman1810/SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

Language: Verilog - Size: 390 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

mwrnd/notes

Various Notes and Tutorials

Language: Tcl - Size: 16.4 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 7 - Forks: 1

xshele01/Digital-electronics-1

Digital Electronics 1 course at Brno University of Technology

Language: VHDL - Size: 30.3 MB - Last synced: about 2 months ago - Pushed: about 3 years ago - Stars: 0 - Forks: 3

vacagonzalo/soc-workflow-vhdl

Example workflow project for VHDL development.

Language: VHDL - Size: 12.7 KB - Last synced: 2 months ago - Pushed: about 1 year ago - Stars: 1 - Forks: 0

themperek/cocotb-vivado

Limited python / cocotb interface to Xilinx Vivado XSIM simulator.

Language: Python - Size: 30.3 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 14 - Forks: 1

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.1 MB - Last synced: 2 months ago - Pushed: 10 months ago - Stars: 27 - Forks: 9

Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

Language: Java - Size: 3.39 MB - Last synced: 2 months ago - Pushed: over 6 years ago - Stars: 15 - Forks: 1

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Language: SystemVerilog - Size: 820 KB - Last synced: about 2 months ago - Pushed: over 4 years ago - Stars: 248 - Forks: 53

tymonx/virtio

Virtio implementation in SystemVerilog

Language: SystemVerilog - Size: 44.9 KB - Last synced: about 2 months ago - Pushed: over 6 years ago - Stars: 44 - Forks: 9

mwrnd/innova2_xcku15p_ddr4_bram_gpio

XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA

Language: Tcl - Size: 6.91 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 12 - Forks: 2

Abdelrahman1810/SPI-Slave-with-Single-Port-RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

Language: Verilog - Size: 600 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

pavel-demin/usb104-a7-notes

Notes on the USB104 A7 development board

Language: Tcl - Size: 1.11 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 0 - Forks: 0

kartikeya443/labwork_LNMIIT

Compilation of my laboratory work based on topics like signal processing, digital communication, computer networks, etc. implemented using languages like MATLAB, VHDL and C++, compiled on MATLAB, Xilinx's Vivado and Omnet++, documented using LaTeX.

Language: SuperCollider - Size: 25.1 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

ichi4096/vivado-on-silicon-mac

Installs Vivado on M1/M2 macs

Language: C - Size: 179 KB - Last synced: 3 months ago - Pushed: 5 months ago - Stars: 171 - Forks: 14

z4yx/vivado-docker Fork of BBN-Q/vivado-docker

Dockerfile with Vivado for CI

Language: Dockerfile - Size: 15.6 KB - Last synced: 3 months ago - Pushed: about 4 years ago - Stars: 27 - Forks: 9

diluo1999/tic_tac_toe

Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.

Language: VHDL - Size: 38.9 MB - Last synced: 3 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

rogermiranda1000/Vivado_PS-PL_data_exchange

Creating a Custom IP for PS-PL data exchange in Vivado

Language: VHDL - Size: 5.32 MB - Last synced: 15 days ago - Pushed: 7 months ago - Stars: 4 - Forks: 0

pavel-demin/giga-zee-notes

Notes on the GigaZee modules

Language: C - Size: 289 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 4 - Forks: 0

ZeroX29a/PynqZ2

Complete collection of general resource of Pynq Z2

Language: Tcl - Size: 67 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

dsa-shua/FPGA-SystolicArray

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

Language: SystemVerilog - Size: 1.59 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

KayeJD/NexysA7-FPGA-Programming

Embedded Programming Projects

Language: Tcl - Size: 56.6 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

sergioverzeichnis/Elevator--FPGA

Language: VHDL - Size: 20.5 KB - Last synced: 3 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced: 15 days ago - Pushed: almost 6 years ago - Stars: 21 - Forks: 2

damian95a/Analog-signal-generator

FPGA based analog signal generator with DAC

Language: Verilog - Size: 461 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

AzazHassankhan/FPGA-IntelligenceSuite

Welcome to the "Machine Learning Models FPGA" repository! 🌟This project showcases the fusion of cutting-edge machine learning techniques with the power of Field-Programmable Gate Arrays (FPGAs). Our goal is to harness the capabilities of FPGA hardware to accelerate and optimize machine learning model deployment.

Language: Jupyter Notebook - Size: 33.4 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

d953i/Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

Language: Tcl - Size: 28.6 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 28 - Forks: 17

2uger/petalinux_notes

Language: SystemVerilog - Size: 10.7 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 2 - Forks: 0

dariusur/SpectrumAnalyzer

FPGA-based real-time audio spectrum analyzer.

Language: VHDL - Size: 54.8 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

li3tuo4/rc-fpga-zcu

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

Language: Tcl - Size: 79.9 MB - Last synced: 3 months ago - Pushed: about 1 year ago - Stars: 50 - Forks: 15

Jrvvv/simple-risc-v-cpu

Developing RISC-V CPU

Language: SystemVerilog - Size: 531 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

yaxsomo/IRIS_CubeSat

This Repository is dedicated to FPGA development of the IRIS CubeSat

Language: VHDL - Size: 88.4 MB - Last synced: 3 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

giuseppericcio/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102 Fork of LaErre9/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102

Workflow for executing CNN Networks on Zynq Ultrascale+ with Vitis AI toolchain. Detailed analysis, configuration and execution of Convolutional Neural Networks on ZCU102 using Vitis AI, evaluating performance on the board compared to Cloud infrastructure (eg. Kaggle). Developed for educational exam purposes.

Language: Jupyter Notebook - Size: 252 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1 - Forks: 0

GitHub topics: vivado