pc2/sus-compiler

A new Hardware Design Language that keeps you in the driver's seat

Language: Rust - Size: 21.3 MB - Last synced at: about 12 hours ago - Pushed at: about 16 hours ago - Stars: 116 - Forks: 7

ab-ff/Multi-Bit-Comparator

Variations of a multi-bit generalized comparator for different area and timing.

Size: 1000 Bytes - Last synced at: about 16 hours ago - Pushed at: about 18 hours ago - Stars: 0 - Forks: 0

Xilinx/Vitis_Accel_Examples

Vitis_Accel_Examples

Language: Makefile - Size: 107 MB - Last synced at: 4 days ago - Pushed at: 2 months ago - Stars: 559 - Forks: 220

calyxir/calyx

Intermediate Language (IL) for Hardware Accelerator Generators

Language: Rust - Size: 513 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 551 - Forks: 60

dohuyminhdung/PQC_Dilithium

Language: SystemVerilog - Size: 94.7 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1 - Forks: 0

JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Language: VHDL - Size: 76.6 MB - Last synced at: 10 days ago - Pushed at: 11 days ago - Stars: 677 - Forks: 54

geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

Language: Verilog - Size: 11.6 MB - Last synced at: 6 days ago - Pushed at: over 4 years ago - Stars: 27 - Forks: 4

ninzzd/RISC-V

Language: Verilog - Size: 130 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 1 - Forks: 0

cornell-zhang/allo

Allo: A Programming Model for Composable Accelerator Design

Language: Python - Size: 5.11 MB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 279 - Forks: 55

pickle-lotus0976/EDA

This repository serves as a personal portfolio and learning log for various FPGA designs. Each top-level folder contains a distinct, self-contained Vivado project. The focus is on creating clean, reproducible, and well-documented hardware designs.

Language: C - Size: 68.4 KB - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 0

KeertiAM29/traffic-light-controller-verilog.

A Verilog-based FSM project that simulates a traffic light controller for a two-way intersection. Includes testbench simulation, timing control, and FPGA implementation using Xilinx tools.

Size: 95.7 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

Awais-Asghar/FPGA-Based-Smart-Car-Security-System

A Smart Anti-Theft Car Security System implemented on FPGA to detect and prevent unauthorized access. The system uses real-time monitoring and control logic to enhance vehicle safety and response.

Language: Verilog - Size: 17.5 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

Korobonshi/VHDL_ROMLESS_DDFS

This repository contains the VHDL implementation of a ROM-less Direct Digital Frequency Synthesizer (DDFS) designed for high-speed calculation of the arctan function. This project was developed as a final assignment to fulfill the requirements for a bachelor's degree in my Electrical Engineering.

Language: VHDL - Size: 29.6 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

topologicalhurt/Thesis

Fpga thesis project. An intelligent hardware scheduling algorithm focused on common signal chains.

Language: Python - Size: 131 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1 - Forks: 1

cucapra/dahlia

Time-sensitive affine types for predictable hardware generation

Language: Scala - Size: 5.59 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 145 - Forks: 8

Alighorbanibargani/AI-based-Neural-Network-Processing-Unit

Welcome to the repository for **Exercise 3 of the AI Systems Course** at the **University of Tehran**. This project focuses on designing and implementing a lightweight, efficient **processing element (PE)** for performing operations of neurons in a **multi-layer perceptron (MLP)** using Verilog.

Language: Verilog - Size: 211 KB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 4 - Forks: 0

koushikb21/pynq_hdmi_passthrough

This project was developed for the ChipIn C2S Hackathon 2025, with the challenge: Real-Time HDMI Image Processing on the PYNQ-Z2 FPGA board. While the ultimate aim was to implement image processing effects, the team successfully implemented a working HDMI passthrough,

Language: Jupyter Notebook - Size: 27.7 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 1

Holandsoest/FPGA_I2C

WIP: An I2C-master AXI-slave, and I2C-Slave. So I can practice myself a bit, and build my own libraries.

Language: VHDL - Size: 313 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

sergz72/FPGA

FPGA related stuff

Language: F# - Size: 6.42 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

hassan-software-dev/PalmPilot-x

Hand Gesture controlled car gamified with a time based checkpoint. Built using Verilog in Vivado with Basys3 FPGA. By M. Hassan Shahid, M. Saad Malik, Sarah Faisal Alvi and S. M. Zaid

Language: Verilog - Size: 43.9 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Zachary-Pearce/Pomegranate

An open source portable and scalable soft-core processor written in VHDL.

Language: VHDL - Size: 2.35 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

jmduarte/HLS_hls4ml_Tutorial

HLS & hls4ml Tutorial

Language: Jupyter Notebook - Size: 16.9 MB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 13 - Forks: 6

tom-zv/FPGA-ESP32-Projects

Projects showcase

Language: VHDL - Size: 261 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

cornell-zhang/heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Language: Python - Size: 38.7 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 340 - Forks: 93

cornell-zhang/HiSparse

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

Language: C++ - Size: 109 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 95 - Forks: 12

Unicamp-Odhin/FPGA_101

Starting in the world of FPGAs!!!!!

Language: Tcl - Size: 18.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

roi-ri/Laboratorio-Sistemas-Digitales-I

Repo para almacenar los laboratorios desarrollados durante el curso de Sistemas Digitales I - IE0323 impartido en la carrera de Ingeniería Eléctrica en la Universidad de Costa Rica (UCR)

Language: Tcl - Size: 17.6 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

Sanugiw/FPGA

UA UART communication module using Verilog on a DE0-Nano FPGA with real-time serial data transfer, and verified functionality with a custom test bench.

Size: 3.49 MB - Last synced at: 9 days ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

manzoorambekar/learning-vhdl

A collection of VHDL projects and exercises for learning digital design, covering basic to intermediate concepts with simulations in ModelSim and synthesis for FPGAs.

Language: VHDL - Size: 9.77 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

TahirZia-1/FPGA-Morse-Code-Encoder

Converts digits (only) into its Morse code on a NEXYS 4 DDR Board, displayed using LED lights. 1 second for dot and 3 seconds for Dash. Can be toggled into different modes for storing digits in FIFO register as well.

Language: HTML - Size: 6.36 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

lebrancconvas/TypeScript-for-Concept

Clarify anything I'm interested in TypeScript until It can't. (Because TypeScript is good and fit to me for mapping out the domain).

Language: TypeScript - Size: 221 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 1

Marisa-Mathew/-Image-Edge-Detection-on-FPGA-Sobel-Filter--Verilog

This project implements real-time edge detection on grayscale images using the Sobel filter algorithm, designed in Verilog and simulated in Xilinx Vivado. A sliding 3×3 window is applied to each pixel to compute gradient magnitudes, highlighting object boundaries.

Language: Verilog - Size: 779 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

OpenEDF/verilog-basic

learn the combinational and sequential logic circuit.

Language: SystemVerilog - Size: 24.3 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 17 - Forks: 1

Skandakm29/uart_loopback

Universal Asynchronous Receiver-Transmitter (UART) loopback on the VSD Squadcom Mini FPGA board

Language: Verilog - Size: 5.45 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

megiemee/chopsticksFPGA

Arcade game implemented in lucid based on the "Chopsticks" game done on Alchitry Labs for 50.002 Computational Structures..

Size: 31.3 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

DebbieMatt/FPGA_VHDL

Objetivo do Projeto Implementação de circuitos digitais em FPGA. Exemplos de lógica combinacional, sequencial e sistemas embarcados. Testes práticos com periféricos (LEDs, botões, displays, etc.).

Language: VHDL - Size: 21.8 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

ThuyPham/FPGA-Toturial

FPGA Tutorial Basic thuypx.com

Language: VHDL - Size: 16.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

rastin-py/NeonBlaster-an-Arcade-Shooting-Game-on-FPGA

An arcade game implemented in VHDL as an assignment for Digital Systems Analysis & Design course at the University of Guilan, Department of Computer Engineering, presented in Fall 2023 by Dr. Mahdi Aminian.

Language: VHDL - Size: 55.3 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

SKpro-glitch/Multi-Bit-Comparator

Variations of a multi-bit generalized magnitude comparator for different area and timing.

Language: D - Size: 275 KB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

amaranth-farm/amgen

command line tool for frequent amaranth HDL tasks (generate sources, show design)

Language: Python - Size: 251 KB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 15 - Forks: 2

OTANK10/FIR-Filter-FPGA-Implementation

Implementing a 4-tap FIR filter on the Intel DE1-SoC FPGA using Verilog HDL

Language: Verilog - Size: 17.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: VHDL - Size: 184 KB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/riscv-on-de2-soc-fpga

A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.

Language: Verilog - Size: 24.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 5 - Forks: 2

SKpro-glitch/Parallel_Multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

Gaby130905/7-segmentos-letras

verilog

Language: SystemVerilog - Size: 8.79 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

HANANDA1/FPGA-Based-Smart-Car-Security-System

FPGA-Based Smart Car Security System is a robust solution for protecting high-end vehicles like Porsche. It uses Verilog and SystemVerilog to detect unauthorized access and disable the fuel pump, ensuring your car remains secure. 🛠️🚗

Language: Verilog - Size: 9.27 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

bilalkabas/Basys3-VHDL-Basics

This repository has basic examples in VHDL using Basys3 board.

Language: VHDL - Size: 39.1 KB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 13 - Forks: 5

jjfumero/tornadovm-examples

Set of examples written for hardware acceleration via TornadoVM

Language: Java - Size: 20.1 MB - Last synced at: 8 days ago - Pushed at: 8 months ago - Stars: 17 - Forks: 5

cornell-zhang/hcl-dialect

HeteroCL-MLIR dialect for accelerator design

Language: C++ - Size: 3.67 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 41 - Forks: 15

nesterovmaxim31/Simpson-s-rule-Verilog

Построение синхронного цифрового автомата для реализации метода Симсона с дальнейшей загрузкой на ПЛИС Artix-7 xс7a100tcsg324-1I

Language: Verilog - Size: 1.36 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

dannyvanderpol/nexys_a7_projects

Projects for the Nexys A7 FPGA development board

Language: Tcl - Size: 4.01 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

jorgeloopzz/Practicas-HP

Prácticas de laboratorio de la asignatura Hardware Programable

Language: Tcl - Size: 1.66 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

rejunity/fpga-icebreaker-racing-the-beam

Playground for graphics experiments running on iCE40 Lattice FPGA with iceBreaker board

Language: Verilog - Size: 40 KB - Last synced at: about 22 hours ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

enriiexposed/das-fdi

Asignatura optativa de la FDI - UCM sobre el diseño de circuitos de tamaño medio usando herramientas de descripcion de hardware automáticas (VHDL, Verilog sobre Vivado)

Language: VHDL - Size: 165 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

pboechat/ice40up5k_riscv Fork of emeb/up5k_riscv

RISC-V SoC on the iCE40UP5K.

Language: C - Size: 540 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

aidinattar/PMOD-FIR-filter-VHDL

Implementation of a FIR-filter on a FPGA and its employment in an audio system obtained using a PMOD I2S2.

Language: SystemVerilog - Size: 91.9 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 1

AnamikaS2005/Audio-based-authentication-system-for-access-control-using-Boolean-FPGA

This project implements a secure, touchless access control system using voice-based authentication on a Boolean FPGA (Spartan-6). It combines Python-generated audio and Verilog-based FPGA design to analyze and compare dominant audio frequencies, allowing access only when the voice patterns match.

Size: 1.68 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/getting-started-with-vhdl

Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.

Language: VHDL - Size: 38.5 MB - Last synced at: 10 days ago - Pushed at: 8 months ago - Stars: 7 - Forks: 0

Choaib-ELMADI/working-with-fpga-and-mips

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.

Language: Verilog - Size: 11.2 MB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 5 - Forks: 0

TahirZia-1/Digital-Clock-Verilog

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Language: Tcl - Size: 283 KB - Last synced at: 9 days ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

2268977258/binocular-stitching

基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后通过匹配结果计算拼接参数，完成图像的拼接。

Language: Verilog - Size: 65.5 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 6 - Forks: 0

MEESAM749/Single-Cycle-Non-Pipelined-MIPS-32-Processor

This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

Language: C - Size: 1.97 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

HarmandeepArneja/ReflexRush

Reaction Time Testing Game

Language: Verilog - Size: 0 Bytes - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/working-with-fpga-and-vhdl

A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.

Language: VHDL - Size: 12.4 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 4 - Forks: 0

pboechat/ice40up5k_tests

Multiple test designs for the iCE40UP5K-B-EVN board.

Language: Verilog - Size: 35.3 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

MistGhost/FPGA-AudioProcessingSystem

2024第八届全国大学生集成电路创新创业大赛获奖作品，基于紫光同创FPGA的音频处理系统。由本人负责的软件部分项目代码工程。

Language: Python - Size: 7.62 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

EngineerMichael/-Robotic-Arm---Haddington-Dynamics-Robotics-Engineering-

⎔ Automation in 3D-Printed Robotics in C & JS (Revising Custom JavaScript Source Code Files)

Language: JavaScript - Size: 4 MB - Last synced at: about 1 month ago - Pushed at: 8 months ago - Stars: 6 - Forks: 0

KietLe11/KLP32-RISCV

This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.

Language: Verilog - Size: 407 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 4 - Forks: 0

Kampi/ZYBO

Miscellaneous things and projects for my ZYBO and ZYNQ devices.

Language: VHDL - Size: 545 MB - Last synced at: 11 days ago - Pushed at: about 2 years ago - Stars: 9 - Forks: 4

Kj0ric/fpga-battleship-game

A digital implementation of the classic Battleship game on the Sipeed Tang Nano 9K FPGA. Features a 4x4 grid with LED and seven-segment displays, two-player support, and best-of-three rounds gameplay.

Language: Verilog - Size: 2.53 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 1

AzuratiX/Realtime-Radar-Using-FPGA-Basys3

This was our final group project. We started with little knowledge about servo control, ultrasonic sensors, or VGA display—but through this project, we learned a lot and were thrilled to see everything work smoothly in the end.

Language: Verilog - Size: 0 Bytes - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

cornell-zhang/GraphLily

A graph linear algebra overlay

Language: C++ - Size: 117 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 51 - Forks: 4

HMarchiori/relogio-xadrez-vhdl

Este projeto implementa um relógio de xadrez utilizando a linguagem VHDL. O sistema gerencia o tempo de jogo de dois jogadores e exibe os tempos restantes em um display.

Language: Tcl - Size: 8.79 KB - Last synced at: 3 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

ClarkFieseln/FPGA_HW_SIM_FWK_2

FPGA Hardware Simulation Framework

Language: Python - Size: 820 KB - Last synced at: 6 months ago - Pushed at: over 2 years ago - Stars: 22 - Forks: 1

TahirZia-1/UART

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

TahirZia-1/RISC-V-CPU-Core-SystemVerilog

This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.

Language: SystemVerilog - Size: 11.9 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

psychogenic/riffpga

riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way

Language: C - Size: 2.42 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 50 - Forks: 3

fm4dd/gatemate-riscv

RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga

Language: Verilog - Size: 6.18 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 12 - Forks: 2

specpose/software-on-silicon

Object oriented, templated building blocks that should be able to run on an fpga. A standard interface for integrating system on chip (SOC).

Language: C++ - Size: 627 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

ahp-electronics/fpga-template

Lattice FPGA Verilog project template

Language: TeX - Size: 115 KB - Last synced at: about 1 month ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Shuregg/FPGA-practicum

learning about FPGA

Language: SystemVerilog - Size: 1.24 MB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Slatyo/SonarTracking

Small project to track things with a waterproof sonar sensor

Language: C++ - Size: 2.22 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

CFZRfrndVolt/Introducing-VHDL-

This repository contains projects and experiments focused on designing, simulating, and implementing digital circuits using VHDL (VHSIC Hardware Description Language) and Quartus II software. The projects covered in this repository serve as an introduction to key concepts in digital system design, including the creation of basic logic circuits, com

Size: 1000 Bytes - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

gundasrikar/FPGA-Verilog-Code-Samples

Language: Verilog - Size: 29.3 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

jakunzler/asic_fpga_introduction

Web page for the ASIC and FPGA Repository

Language: Dockerfile - Size: 63.9 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

GAbeGH/Keypad

FPGA-Based Digital Lock System with Digital Noise Filter

Language: C - Size: 7.83 MB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

ishifr/fpga_prototyping_codes

FPGA prototyping by Verilog examples kitobini o'qish davomida yozilgan kodlar to'plami. Nexys4DDR(Artix-7) dev board'dan foydalanilgan. A collection of code written while reading the book FPGA prototyping by Verilog examples. Nexys4DDR(Artix-7) dev board is used

Language: Tcl - Size: 0 Bytes - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

gabrielvscodee/studying-system-verilog

🔋 SystemVerilog study repository

Language: SystemVerilog - Size: 23.4 KB - Last synced at: 19 days ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

1c3t3a/canny-zybo-z7

Implementation of a Canny-Edge Detector on a Zybo-Z7 FPGA.

Language: VHDL - Size: 115 MB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

mikeroyal/FPGA-Guide

FPGA Guide

Language: Verilog - Size: 25.4 KB - Last synced at: 7 months ago - Pushed at: almost 4 years ago - Stars: 12 - Forks: 2

anupam-io/ES203-COA-CNN

ES-203 Computer Organization & Architecture CNN on FPGA board

Language: Verilog - Size: 16.1 MB - Last synced at: 7 months ago - Pushed at: over 3 years ago - Stars: 12 - Forks: 8

Emibuglioni/Digital_Voltmeter

Language: Jupyter Notebook - Size: 68.4 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

Reallyummy/FPGA_Drawing_WeakNote

This project is a drawing program for Basys3 FPGA board. This code is written for Verilog. Enjoy!!! :)

Language: Verilog - Size: 12.7 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

OP-Patel/Gomoku

Gomoku on a DE1-SoC Board

Language: Verilog - Size: 662 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

ClarkFieseln/FPGA_HW_SIM_FWK

FPGA Hardware Simulation Framework

Language: Python - Size: 2.18 MB - Last synced at: 6 months ago - Pushed at: almost 3 years ago - Stars: 15 - Forks: 2

Wissance/QuickRS232

A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX

Language: Verilog - Size: 739 KB - Last synced at: 6 months ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

YogeshGoyyalA-1/FPGA_PROJECT

This project implements real-time image processing on an Artix-7 FPGA using VGA display. It applies filters like negative, grayscale, and color thresholding to images stored in Block RAM. The filters are controlled via hardware switches, and the processed image is displayed on a VGA monitor.

Language: Tcl - Size: 60.5 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

h0nt3d/modulo2345UpDownCounter

A counter written in VHDL that has been designed to count in radix 8 up and down from 0 to 2344 in radix 14 while displaying the counting on 4 Seven Segment Displays

Language: VHDL - Size: 8.79 MB - Last synced at: 8 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

alisayurev/fpga-vga-mem-game

A rhythm-based memory game implemented on an FPGA. The game displays a sequence of MIDI notes on a screen, which players must mimic to score points. This project combines hardware and game development to create an interactive experience that tests memory and timing, using an FPGA to generate and process MIDI signals in real-time.

Language: VHDL - Size: 2.93 KB - Last synced at: 8 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/fpga-programming-for-beginners

A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.

Language: Tcl - Size: 30.4 MB - Last synced at: 7 months ago - Pushed at: about 1 year ago - Stars: 11 - Forks: 1