GitHub topics: rtl-design
Subbu-kata/KATA_SUBRAMANYAM_G3_INTEGRATED_VLSI
This project is a fully functional Vending Machine Controller designed using Verilog HDL, featuring modular design, multi-clock domain handling, and APB-based configuration. The system supports both configuration and operation modes, allowing real-time selection, purchase, and dispensing of items based on valid currency input.
Size: 1.95 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

pulp-platform/croc
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
Language: SystemVerilog - Size: 59.5 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 73 - Forks: 18

ab-ff/Multi-Bit-Comparator
Variations of a multi-bit generalized comparator for different area and timing.
Size: 1000 Bytes - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Language: Verilog - Size: 31 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 247 - Forks: 64

4xmen/Web-Package-RTL
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
Language: HTML - Size: 19.4 MB - Last synced at: 7 days ago - Pushed at: 6 months ago - Stars: 661 - Forks: 204

HarmandeepArneja/ReflexRush
Reaction Time Testing Game
Language: Verilog - Size: 0 Bytes - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

4xmen/x-tree-select
Tree Select jQuery plugin
Language: JavaScript - Size: 317 KB - Last synced at: 12 days ago - Pushed at: 10 months ago - Stars: 103 - Forks: 27

4xmen/x-mega-menu
x mega menu is repsonsive mega menu based on vannilajs
Language: JavaScript - Size: 1010 KB - Last synced at: 8 days ago - Pushed at: 9 months ago - Stars: 177 - Forks: 46

AUCOHL/RTL-Repo
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
Language: Python - Size: 202 KB - Last synced at: 15 days ago - Pushed at: 11 months ago - Stars: 13 - Forks: 1

SKpro-glitch/Multi-Bit-Comparator
Variations of a multi-bit generalized magnitude comparator for different area and timing.
Language: Verilog - Size: 33.2 KB - Last synced at: 29 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

esynr3z/pip-hdl
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
Language: Python - Size: 55.7 KB - Last synced at: 7 days ago - Pushed at: about 1 year ago - Stars: 7 - Forks: 0

SKpro-glitch/Parallel_Multiplier
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
Language: SystemVerilog - Size: 13.7 KB - Last synced at: 15 days ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

VarshithGovi/Logic_gates
Simulate and analyze fundamental logic gates using Icarus Verilog and GTKWave. This project provides a modular Verilog implementation and a comprehensive testbench for precise validation, offering valuable insights into digital design workflows for VLSI professionals.
Language: Verilog - Size: 33.2 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

ViniMF13/Laboratorio_Sistemas_Digitais
Implementação do Projeto Final da Disciplina de Sistemas Digitais, oferecia pelo Departamento de Engenharia Elétrica da UFMG. O Projeto elabora um sistema de cofre digital, seguindo a metodologia de Resgister Transfer Level.
Language: VHDL - Size: 13.6 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

mrxeg1995/yanbu
نقل عفش بينبع
Language: HTML - Size: 8.92 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

MohamedHussein27/RISC-V-Single-Cycle-Implementation
This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.
Language: Verilog - Size: 11.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

synogate/gatery
Gatery, a library for circuit design.
Language: C++ - Size: 8.29 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 17 - Forks: 5

4xmen/rvnm
Responsive vertical navigation menu
Language: CSS - Size: 11.6 MB - Last synced at: 3 days ago - Pushed at: over 2 years ago - Stars: 65 - Forks: 8

synogate/gatery_template
Template project for using gatery
Language: C++ - Size: 22.5 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 4 - Forks: 1

williaml33moore/bathtub Fork of everactive/bathtub
BDD Gherkin implementation in native SystemVerilog, based on UVM.
Language: SystemVerilog - Size: 7.61 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 2 - Forks: 0

ahmd-kamel/ATM-Bank-Finite-State-Machine
Digital Design & Verification by implementing the core of the bank ATM design as well as verification environment.
Language: C++ - Size: 386 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Haaris-RTL/8-bit-CPU
RTL code of an 8-bit CPU designed in Verilog.
Language: Verilog - Size: 97.7 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 1

Abdelrahman1810/SPI_Slave_with_Single_Port_RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Language: Verilog - Size: 401 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

tom-zv/FPGA-ESP32-Projects
Projects showcase
Language: VHDL - Size: 287 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Khosravi19/SPA-CodeTime
Single-page application of programming courses using React with a panel and login page
Language: JavaScript - Size: 5.07 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

shahed22/Dadda-8-bit
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
Language: Verilog - Size: 11.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/RV32I_5-Stage_Pipelined_CPU
Processor Design of RV32I 5-Stage Pipelined CPU
Language: SystemVerilog - Size: 170 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/RV32I_Single_Cycle_CPU
Processor Design of RV32I Single Cycle CPU
Language: SystemVerilog - Size: 590 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/AXI4
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
Language: Verilog - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Abdelrahman1810/SPI-Slave-with-Single-Port-RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Language: Verilog - Size: 600 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/ARTY_A7_I2C_MPU-6050
Integration of Arty A7-100T with MPU-6050 Gyroscope Sensor for Motion Sensing and FPGA Testing
Language: Verilog - Size: 218 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/ARTY_A7_I2C_BME280
Integration of Arty A7-100T with BME280 Pressure Sensor for Pressure Sensing and FPGA Testing
Language: Verilog - Size: 772 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ZAIN-ALI-02/UART
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
Language: Verilog - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/I2C
RTL Design of Inter-Integrated Circuit
Language: Verilog - Size: 538 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Ammar-Bin-Amir/SPI
RTL Design of Serial Peripheral Interface
Language: Verilog - Size: 451 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/UART
RTL Design of Universal Asynchronous Receiver-Transmitter
Language: Verilog - Size: 990 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

alirezajaberirad/Object-Oriented-Modeling-of-Electronic-Circuits
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
Language: C++ - Size: 7.06 MB - Last synced at: 12 months ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

cp024s/100-days-of-RTL
probable journey of RTL coding ft. Chandra Prakash
Language: Verilog - Size: 292 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

gabrielganzer/RTSNoC-Sniffer
Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.
Language: C++ - Size: 29.3 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 0

maazm007/100Daysof_RTL
The Repository contains the code of various Digital Circuits
Language: Verilog - Size: 20.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 1

farukyld/sort-circuit
an RTL circuit that sorts the integer values in a momory unit connected with AXI-Lite
Language: Verilog - Size: 2.5 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

sidhantp1906/AMBA4-APB
Advanced Pheripheral Bus design using verilog HDL
Language: Verilog - Size: 348 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 1

Luca-Dalmasso/DLX
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
Language: Verilog - Size: 16.3 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 1

snbk001/100DaysofRTL
100DaysofRTL: basic logic gates, mux, half and full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector with Moore, Edge Detector with Mealy
Language: SystemVerilog - Size: 120 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 2

diluo1999/tic_tac_toe
Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.
Language: VHDL - Size: 38.9 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Farbod-Siahkali/Digital-Logical-Designs-Projects
Digital Logical Designs Course Projects
Language: Verilog - Size: 4.66 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Luca-Dalmasso/RISCV_LBIST Fork of alessandrolandra/RISCV_LBIST
Design of a BIST module for RISC-V fault testing
Size: 60.2 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Luca-Dalmasso/Max-Pooling_VHDL
HLSM with memory design for max pooling algorithm.
Language: VHDL - Size: 1.71 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

wolfdroid/Integer_Calculator
Simple RTL model for Interger Numbers Calculation using RAM and 7 Segment Display.
Language: VHDL - Size: 1.79 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0
