GitHub topics: testbench-verification
Haaris-RTL/8-bit-CPU
RTL code of an 8-bit CPU designed in Verilog.
Language: Verilog - Size: 97.7 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 1
Nistha632/UVM-ALU
ALU (4 modes of operation)
Language: SystemVerilog - Size: 21.5 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
ZAIN-ALI-02/UART
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
Language: Verilog - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
