GitHub topics: testbench-verification
OTANK10/FIR-Filter-FPGA-Implementation
Implementing a 4-tap FIR filter on the Intel DE1-SoC FPGA using Verilog HDL
Language: Verilog - Size: 17.6 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0
Madhu-Krishnan-A-P/mux
This repository contains the Verilog design and testbench for a 4x1 Multiplexer. It uses two select lines to choose one of the four inputs (A0–A3) and drive it to a single output based on the logic expression: Y = S1’S0’A0 + S1’S0A1 + S1S0’A2 + S1S0A3
Language: Verilog - Size: 2.93 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
Haaris-RTL/8-bit-CPU
RTL code of an 8-bit CPU designed in Verilog.
Language: Verilog - Size: 97.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 1
Nistha632/UVM-ALU
ALU (4 modes of operation)
Language: SystemVerilog - Size: 21.5 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0
ZAIN-ALI-02/UART
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
Language: Verilog - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
