GitHub topics: behavioural-simulation
Madhu-Krishnan-A-P/decoder
Implements a 3-to-8 line decoder using gate-level logic in Verilog. Converts a 3-bit binary input into a corresponding one-hot output across 8 lines (D0–D7). Features: Gate-level realization, Truth table-based logic equations, Behavioral simulation with 8 input combinations
Language: Verilog - Size: 1.08 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
Madhu-Krishnan-A-P/mux
This repository contains the Verilog design and testbench for a 4x1 Multiplexer. It uses two select lines to choose one of the four inputs (A0–A3) and drive it to a single output based on the logic expression: Y = S1’S0’A0 + S1’S0A1 + S1S0’A2 + S1S0A3
Language: Verilog - Size: 2.93 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0