briansune/FPGA-Camera-MIPI-DVP-Verilog

FPGA Camera Parallel & MIPI Verilog

Size: 60.5 KB - Last synced at: about 3 hours ago - Pushed at: about 5 hours ago - Stars: 25 - Forks: 2

marcelwa/aigverse

A Python library for working with logic networks, synthesis, and optimization.

Language: Python - Size: 1.79 MB - Last synced at: about 5 hours ago - Pushed at: about 6 hours ago - Stars: 65 - Forks: 3

avaycele/TangNano9K-Frenzy

🎮 Port Frenzy Arcade VHDL code to Tang Nano 9K FPGA for seamless VGA monitor compatibility, enhancing your gaming experience effortlessly.

Language: Shell - Size: 1.82 MB - Last synced at: about 13 hours ago - Pushed at: about 14 hours ago - Stars: 0 - Forks: 0

JuanCantu1/fpga-trumpet-dsp

Real-time trumpet audio enhancement system with note detection, frequency analysis, and live DSP effects implemented across the DE1-SoC’s ARM processor and Cyclone V FPGA.

Language: Python - Size: 16.1 MB - Last synced at: about 16 hours ago - Pushed at: about 16 hours ago - Stars: 2 - Forks: 0

ShekharShwetank/ASIC_Design

ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.

Language: Verilog - Size: 156 MB - Last synced at: about 16 hours ago - Pushed at: about 17 hours ago - Stars: 2 - Forks: 0

EmilPopovic/simple-axi-master

A general purpose AXI4 master module for FPGA designs using PYNQ-Z2.

Language: Tcl - Size: 8.79 KB - Last synced at: about 21 hours ago - Pushed at: about 21 hours ago - Stars: 0 - Forks: 0

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 19.9 MB - Last synced at: about 22 hours ago - Pushed at: about 22 hours ago - Stars: 1,555 - Forks: 164

0BAB1/HOLY_CORE_COURSE

Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with schemes & explanation.

Language: Python - Size: 23.1 MB - Last synced at: about 21 hours ago - Pushed at: about 23 hours ago - Stars: 251 - Forks: 30

qqqrrt/FIR_Fliter_design_and_signal_flow

使用verilog HDL 設計n抽頭 FIR Filter 電路，使用Matlab計算並產生n抽頭係數，並且圖形驗證Filter

Language: Verilog - Size: 4.88 KB - Last synced at: about 23 hours ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

DrSkyFire/Odyssey

基于FPGA的高性能双通道信号分析与自动测试系统 | 35MSPS双通道采样 | 8192点FFT频谱分析 | 数字锁相放大微弱信号检测 | 自动测试 | HDMI 720p实时显示

Language: Verilog - Size: 40.9 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1 - Forks: 0

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 3 - Forks: 0

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 81.6 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 822 - Forks: 48

miguelmagv/verilog-flm

⚙️ Simplify Verilog design and simulation with verilog-flm, a lightweight framework that enhances your workflow and boosts productivity.

Size: 1.29 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

codegauravb7/verilog-toUpper

CSC 211000 Project 1 — Gate-level toUpper in Verilog with delays, tests, and report

Language: Verilog - Size: 7.31 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 12.9 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 346 - Forks: 84

verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Language: C++ - Size: 351 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,160 - Forks: 430

Kilo9000/TangNano9K-Apple1

🖥️ Port Apple 1 computer code to Tang Nano 9K FPGA for seamless VGA monitor experience, leveraging original work by Alan & Niels for easy access and enjoyment.

Language: Verilog - Size: 1.76 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

The-OpenROAD-Project/OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Language: Verilog - Size: 840 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 510 - Forks: 391

hsgofficial/TangNano9K-Gottlieb_MA55

🐙 Tang Nano 9K port of Gottlieb MA55 sound board. VHDL code ported to FPGA with work by James Sweet; open hardware for arcade audio.

Language: VHDL - Size: 487 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 3 - Forks: 0

sadadsh/risc-v-processor-fpga

A computer engineering student created performance-optimized RISC-V processor implementation using the ZYNQ 7000 Series Z7-20 FPGA, including intelligent power management and adaptive branch prediction along with statistics. Coded in Verilog-HDL with AMD Vivado.

Language: Verilog - Size: 261 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

heyfey/sv-pathfinder

VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

Language: TypeScript - Size: 16.4 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 29 - Forks: 0

RarityBrown/blog

Some ramblings about my major. 一些有关我的专业的碎碎念

Language: Shell - Size: 1.19 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 3 - Forks: 1

ravez24/verilog-c2w

🎛️ Convert Verilog code to C for efficient simulation and synthesis, streamlining design workflows and enhancing hardware development processes.

Size: 1.29 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 1

Stephanie758/Half_Adder_Verilog_Code_Xilinx_Vivado

🔧 Explore Verilog code for a Half Adder with testbench and simulation results, designed for Xilinx Vivado. Perfect for learning digital design fundamentals.

Language: JavaScript - Size: 1.62 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Language: C - Size: 24.5 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 4,400 - Forks: 735

shishir-dey/asic-mppt

ASIC implementation of a Maximum Power Point Tracking (MPPT) controller

Language: Verilog - Size: 24.4 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

TatsuProject/chipforge_eda_server

EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

Language: Python - Size: 32.3 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

chaseruskin/orbit

Package manager and build system for VHDL, Verilog, and SystemVerilog

Language: Rust - Size: 63 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 57 - Forks: 2

LSC-Unicamp/processor_ci

Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

Language: SystemVerilog - Size: 1.95 MB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 12 - Forks: 1

The-OpenROAD-Project/OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Language: Verilog - Size: 837 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 2,253 - Forks: 728

Joshvareba11/model-memory-calculator

📊 Estimate memory usage for GGUF models in your browser, using local files or remote URLs, with no server needed and seamless performance.

Language: HTML - Size: 1.31 MB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

joseph-kivuva/TangNano9K-Arcade

🎮 Build your own arcade experience with the Tang Nano 9K Arcade PCB, featuring 8-bit VGA, PS2 keyboard support, and dual-channel audio.

Size: 2.17 MB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

robinlebon/TangNano9K-Centipede

🎮 Port Centipede arcade VHDL code to the Tang Nano 9K FPGA Board for seamless VGA monitor integration by Pinballwiz.org.

Language: Verilog - Size: 1.83 MB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

Nic30/hwtLib

hardware library for hwt (= ipcore repo)

Language: Python - Size: 6.68 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 43 - Forks: 7

Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Language: Python - Size: 19.2 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 218 - Forks: 29

Nic30/hdlConvertorAst

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Language: Python - Size: 801 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 41 - Forks: 11

google/xls

XLS: Accelerated HW Synthesis

Language: C++ - Size: 71.2 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,362 - Forks: 213

xlsynth/bedrock-rtl

High quality and composable RTL libraries in SystemVerilog

Language: SystemVerilog - Size: 4.01 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 28 - Forks: 4

alikhaled14589653/DE2-MissileCommand

Missile Command Arcade synthesized on an Altera DE2-35 Dev Board.

Language: Verilog - Size: 246 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

Rushikesh321/adder

Event-driven tool/library for tailing the Cardano blockchain blockchain, cardano, ouroboros, ouroboros-network, toolbox

Language: Go - Size: 109 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 1

dridino/RVV

Vector extension implementation for a RISCV core

Language: Verilog - Size: 3.74 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

SpinalHDL/SpinalHDL

Scala based HDL

Language: Scala - Size: 81.7 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,869 - Forks: 362

Brandon-git-hub/TechBlog

Tech Blog

Language: Python - Size: 6.9 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

shobhit-mittra/baseband_processor

Design of a simple base-band processor using Verilog HDL and hardwaree implementation of Spartan-7 fpga unit, as a part of the HDL Chip Design Laboratory at TUM

Language: Verilog - Size: 27.3 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

amba230/TangNano9K-Galaga

Language: VHDL - Size: 1.84 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

logisim-evolution/logisim-evolution

Digital logic design tool and simulator

Language: Java - Size: 110 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 6,427 - Forks: 807

verilator/verilator

Verilator open-source SystemVerilog simulator and lint system

Language: C++ - Size: 63.9 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 3,155 - Forks: 713

Gonsukey/verilog-uhj

🛠️ Streamline your hardware design with Verilog-UHJ, an efficient framework for creating and managing digital circuit simulations.

Size: 1.29 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

SuggarGrandma420/Router-1x3

🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.

Language: JavaScript - Size: 16.4 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

soltana11/TangNano9K-Invaders2

Tang Nano 9K Space Invaders Part II ports a VHDL arcade game to the Tang Nano 9K FPGA, playable on VGA displays 🐙.

Language: VHDL - Size: 562 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 2 - Forks: 0

Bhonesh/power-optimized-riscv

⚙️ Optimize power consumption with a 3-stage pipelined RISC-V processor, designed for energy efficiency through advanced clock and data gating techniques.

Language: Verilog - Size: 1.48 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 1

soni3006/basic_logic_gates_with_verilog

basic logic gates are implemented using verilog languege and simulation is done in xilinx vivado

Language: JavaScript - Size: 75.2 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

autohdw/pytv

Python Templated Verilog

Language: Rust - Size: 281 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 3 - Forks: 2

TalesNogueira/Unicycle-MIPS-Based-Computer-System

A Unicycle MIPS-based computer system implementing a RISC architecture, designed to execute instructions generated by a C- Compiler.

Language: Verilog - Size: 19.5 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

chipsalliance/chisel

Chisel: A Modern Hardware Design Language

Language: Scala - Size: 160 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 4,460 - Forks: 641

nikolozi93/verilog-3ai

🔧 Simplify Verilog design with AI-driven tools for automated code generation, validation, and optimization in digital circuit projects.

Size: 1.29 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 1

metr0jw/Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA

FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch

Language: Verilog - Size: 396 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 85 - Forks: 6

WangXuan95/FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Language: Verilog - Size: 75.2 KB - Last synced at: 3 days ago - Pushed at: about 2 years ago - Stars: 213 - Forks: 36

adilsondias-engineer/fpga-learning

Learning FPGA development for low-latency trading systems. Projects progress from fundamentals to trading-relevant concepts like high-speed data processing, protocol implementation, and hardware acceleration.

Language: VHDL - Size: 61.6 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

dalance/svlint

SystemVerilog linter

Language: Rust - Size: 4.35 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 365 - Forks: 43

cocotb/cocotb

cocotb: Python-based chip (RTL) verification

Language: Python - Size: 9.87 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 2,131 - Forks: 590

cocotb/cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Language: Python - Size: 5.95 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 70 - Forks: 49

wyvernSemi/riscV

Open source ISS and logic RISC-V 32 bit project

Language: C++ - Size: 75.2 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 61 - Forks: 15

krynentechnology/soneo

SONEO is an SR2CB application for digital audio distribution

Language: Verilog - Size: 1.26 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 1

furrtek/SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

Language: Verilog - Size: 635 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 197 - Forks: 15

stnolting/neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Language: VHDL - Size: 908 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 84 - Forks: 33

cyril0124/verilua

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Language: Lua - Size: 4.66 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 6 - Forks: 0

Essenceia/blake2s

Rework of blake2. Optimized for area ahead of an asic tapeout. Supporting block streaming and using a key. Focused design and verification effort on the blake2s variant.

Language: Verilog - Size: 1.66 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

dbdan114/Verilog

Make Some CMOS Circuits

Language: Verilog - Size: 144 KB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

martonbognar/vcdvis

VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.

Language: Python - Size: 81.1 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 31 - Forks: 6

viktor-prutyanov/drec-fpga-intro

Материалы для курсов по проектированию цифровых вычислительных систем

Language: Verilog - Size: 14.3 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 97 - Forks: 35

ponto-de-vista/digital-circuits

Verilog & LTspice

Language: Verilog - Size: 32.2 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 0

siliconcompiler/siliconcompiler

Modular hardware build system

Language: Python - Size: 342 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1,099 - Forks: 112

freand76/digsim

An interactive digital logic simulator with verilog support (Yosys)

Language: Python - Size: 1.59 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 25 - Forks: 0

curiousGuy101/vhdl-7yh

🔧 Simplify digital design with VHDL in this efficient and user-friendly library tailored for quick implementation and enhanced project management.

Size: 7.81 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

AUDIY/Questa_Verification_Tutorials

Examples for the Questa本 (Tentative)

Language: Verilog - Size: 43 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

loykylewong/FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Language: Scala - Size: 3.21 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 132 - Forks: 31

ostival/ostival-desktop

Open Source Desktop Application for Verilog to GDSII Flow

Language: C++ - Size: 912 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 3 - Forks: 0

zachjs/sv2v

SystemVerilog to Verilog conversion

Language: Haskell - Size: 1.94 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 670 - Forks: 60

MCasoni-reborn/vhdl-4my

⚙️ Streamline your VHDL workflows with vhdl-4my, a tool designed for efficient design, testing, and visualization of VHDL projects.

Size: 1.29 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

RonnyA/nd-120

Norsk Data ND-120 CPU Design Documents. Modern Logisim and HDL implementation

Language: Verilog - Size: 221 MB - Last synced at: about 18 hours ago - Pushed at: about 20 hours ago - Stars: 10 - Forks: 1

aibarr23/Embedded-Control-Robotics

Everything Embedded to FPGA including RTOS and ROS2

Language: C - Size: 26.3 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

dau-dev/verilator-python

Python/PyPI wrapper for Verilator

Language: Python - Size: 104 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 4 - Forks: 0

kdridi/nandland

Apprendre le développement FPGA avec la Go Board : 25 exercices progressifs de logique combinatoire aux projets avancés (TDD, 100% CLI)

Language: Verilog - Size: 42 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

hankhsu1996/slangd

SystemVerilog language server based on Slang frontend

Language: C++ - Size: 1.06 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 2 - Forks: 0

nickg/nvc

VHDL compiler and simulator

Language: C - Size: 26.9 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 749 - Forks: 95

jasonyu1996/anvil

Language: OCaml - Size: 1.08 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 15 - Forks: 1

chili-chips-ba/wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Language: Verilog - Size: 1.98 GB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1,234 - Forks: 27

iammituraj/fifo

Synchronous FIFOs designed in Verilog/System Verilog.

Language: SystemVerilog - Size: 78.1 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 19 - Forks: 8

michael-lehn/ulm-on-ice

ULM (Ulm Lecture Machine) on ice40

Language: SystemVerilog - Size: 45.6 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 6 - Forks: 0

menotti/aoc

Arquitetura e Organização de Computadores usando RISC-V

Language: SystemVerilog - Size: 5.1 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 7 - Forks: 4

analogdevicesinc/hdl

HDL libraries and projects

Language: Verilog - Size: 106 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1,768 - Forks: 1,604

wyvernSemi/pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities

Language: C - Size: 7.04 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 122 - Forks: 26

msinger/gbreveng

Stuff for Gameboy reverse engineering and some documentation

Language: SystemVerilog - Size: 143 MB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 5 - Forks: 0

F0ka/Pipelined-Five-Stage-RISC-V-Core-in-Verilog

The aim of this study is to design and implement a RISC-V core with a pipelined architecture in Verilog HDL. While the core design has been successfully implemented, the hazard management unit remains under development. This article details the implementation approach, the challenges faced, and the results achieved thus far.

Language: Verilog - Size: 11.7 KB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

FPGAwars/apio

:seedling: Open source ecosystem for open FPGA boards

Language: Python - Size: 149 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 905 - Forks: 152

forestfoxx/awesome-hardware-fuzzing

A curated list of research and repositories on the novel technique of hardware fuzzing

Size: 175 KB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 12 - Forks: 3

Pconst167/sol-1

Sol-1: A CPU/Computer System made from 74 series logic.

Language: C - Size: 897 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 78 - Forks: 4

pkpkp456/Learn_System_Verilog

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

Language: Jupyter Notebook - Size: 24.3 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0