GitHub topics: adder | Ecosyste.ms: Repos

Rushikesh321/adder

Event-driven tool/library for tailing the Cardano blockchain blockchain, cardano, ouroboros, ouroboros-network, toolbox

Language: Go - Size: 109 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

saifalisew1508/Telegram-Members-Adder

Telegram Members Adding Software/Script Using Termux.

Language: Python - Size: 199 KB - Last synced at: 7 days ago - Pushed at: about 2 months ago - Stars: 641 - Forks: 158

Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.

Language: Python - Size: 36.1 KB - Last synced at: 14 days ago - Pushed at: almost 2 years ago - Stars: 596 - Forks: 280

Tamoziit/Computer-Architecture-Organisation-Lab

Vivado VHDL

Language: VHDL - Size: 22.5 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 0 - Forks: 0

xbkdf2819/Telegram-Members-Adder

Telegram Members Adding Software/Script for free. Scrape more than 10k Telegram members and add members to your group.

Size: 34.2 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 226 - Forks: 4

2268977258/32-bit-Floating-Point-Adder

32位单精度浮点数加法器是一种专门用于执行符合IEEE 754标准的32位单精度浮点数加法运算的数字电路。这种加法器在现代计算机系统中扮演着重要角色，特别是在处理需要高精度计算的任务时，如科学计算、图形处理、机器学习等应用领域。这个小项目实现了一个符合IEEE 754 单精度浮点数标准（32 位）的浮点数加法器的完整设计。该设计的目标是通过Verilog实现一个能够处理两输入浮点数的加法运算模块。

Language: Verilog - Size: 257 KB - Last synced at: 25 days ago - Pushed at: about 2 months ago - Stars: 4 - Forks: 0

nitrece/digital-electronics-laboratory

Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices that use or produce them.

Size: 10.1 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

antonblanchard/vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Language: Python - Size: 3.02 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 112 - Forks: 9

Bharadwaj-R/Basic-Verilog-Codes

Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.

Language: Verilog - Size: 21.5 KB - Last synced at: 22 days ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

Psingh12354/HackerRank-Certification

HackerRank Certification Question

Language: Python - Size: 35.2 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 97 - Forks: 116

Zannatul-Naim/Digital-System-Design

Digital System Design Lab Codes using Verilog

Language: Verilog - Size: 52.7 KB - Last synced at: 22 days ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

NikosDelijohn/ksa

A synthesizable and modular Kogge-Stone Adder (KSA) implementation in SystemVerilog.

Language: SystemVerilog - Size: 81.1 KB - Last synced at: about 2 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

dragonish/huma-rime-adder

基于虎码秃版方案的 Rime 加词器

Language: Python - Size: 253 KB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

VarshithGovi/2bit-Ripple-Carry-Adder-Verilog

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

Language: Verilog - Size: 25.4 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

joedebiden/Telegram-scraper-adder-app

A free app for telegram scraping, adder, message sender, proxy manager, all in one and over optimized.

Language: Python - Size: 28.4 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Damantha126/TelegramScraper

Using this tool you can easily add so many members from any group to your group. Less than 2 minutes. Super easy. Time saver. But this tool is only for educational purpose. You could be banned from Telegram. So be careful. Recommanded to use this tool only on Termux.

Language: Python - Size: 25.4 KB - Last synced at: about 6 hours ago - Pushed at: almost 4 years ago - Stars: 15 - Forks: 11

Shiritai/aias-lab4-spring-2024

Lab4 of AI computing Architecture and System (2024 spring) around basic chisel design

Language: Scala - Size: 31.3 KB - Last synced at: 2 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

ayusdixit/Digital-ASIC-LAB

Verilog Codes for various Design

Language: SystemVerilog - Size: 1.38 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 2

RaulMurillo/Flo-Posit

Posit Arithmetic Cores generated with FloPoCo

Language: VHDL - Size: 467 KB - Last synced at: 2 months ago - Pushed at: 12 months ago - Stars: 24 - Forks: 8

prosenjitjoy/4-bit-PC

Proteus implementation of 4 bit PC

Size: 297 KB - Last synced at: 2 months ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

mongrelgem/Verilog-Adders

Implementing Different Adder Structures in Verilog

Language: Verilog - Size: 77.1 KB - Last synced at: 4 months ago - Pushed at: almost 6 years ago - Stars: 60 - Forks: 16

shane-staret/SimpleBinaryCalculator

A Java binary calculator based on a system of gates

Language: Java - Size: 24.4 KB - Last synced at: 3 months ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 1

DenizShabani/telegramscraper

Scraper and adder for Telegram supporting multiple accounts at the same time. Adds via Telegram API and only by username. For adding via ID and not needing Telgram API contact me.

Language: Python - Size: 17.6 KB - Last synced at: 7 months ago - Pushed at: about 2 years ago - Stars: 371 - Forks: 168

aleksibovellan/numberAdder

A simple C# number adder made for testing and learning purposes. First school project.

Language: C# - Size: 9.77 KB - Last synced at: 3 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

evilbream/TG_adder_with_proxy

Telegram Group Parser/Scraper and user Adder via id or username with proxy support

Language: Python - Size: 103 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 34 - Forks: 7

Nidhinchandran47/flotadder

This is the VHDL code for a floating point adder

Language: VHDL - Size: 86.9 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 3 - Forks: 0

sathish-a/BinaryAdder

A model to do binary addition

Language: Jupyter Notebook - Size: 179 KB - Last synced at: 10 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

HidayetSelimASAN/Recursive-Adder-Tree-Implementation-in-VHDL

A module to calculate the sum of n number of inputs in adder tree format

Language: VHDL - Size: 8.79 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

gubbriaco/digital-electronics-projects

Progetti di Elettronica Digitale 2021.

Language: VHDL - Size: 7.01 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

mattvenn/instrumented_adder

Instrumenting adders to measure speed

Language: Verilog - Size: 13.1 MB - Last synced at: 4 days ago - Pushed at: almost 3 years ago - Stars: 13 - Forks: 3

OfficialPixelBrush/PASS-2-4

A Diode-Transistor-Logic Adder System built from Scratch, with simplicity and robustness in mind

Size: 1.4 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

utkarshad21/4-bit-Full-Adder-using-Verilog-HDL

Verilog code and testbench for 4-bit full adder

Language: Verilog - Size: 5.86 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

rafidmuhammad/vhd-adder4

4-bit adder with outputs consists of sum and carry out

Language: VHDL - Size: 1.95 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

gokberkkeptig/Full-Adder

An adder is a digital circuit that performs addition of numbers. Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.

Language: C - Size: 96.7 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

svelte-compose/svelte-compose 📦

⚠️ MOVED: https://github.com/svelte-add/svelte-add/ ⚠️ Add different tools to your new or existing svelte / svelte-kit project

Language: TypeScript - Size: 285 KB - Last synced at: 9 days ago - Pushed at: about 1 year ago - Stars: 8 - Forks: 0

mohammadreza-babaeimosleh/FPU_Add_Unit_VHDL

In this project we have implemented Add/Minus unit and operations in a Floating-Point unit

Language: C - Size: 2.25 MB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

SanjaySunil/LicenseMe

🏷 Your handy tool for licensing and protecting your code.

Language: Python - Size: 135 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

SoloSynth1/8BitCLA

Verilog for low delay 8-bit CLA with 4-bit lookahead circuits

Language: Verilog - Size: 198 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

BeyondGoodAndDev/doublegram_community_edition

Super complete Scraper-Adder for Telegram with innovative functions. Check the website!

Language: Python - Size: 59.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

CodiieSB/VHDL-Half_Adder

A half adder is a digital circuit that performs addition of two binary digits, generating the sum bit and the carry bit.

Language: VHDL - Size: 66.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

datatachyons/Telegram-Adding-Tool-2024

Tool to export members from Telegram Groups and Channels to a CSV file and to add them to Telegram Groups or Channels an DM

Size: 167 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

iulianoroberto/JavaRMI_Adder

Simple RMI application used to sum two numbers, client/server architecture.

Language: Java - Size: 129 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

mosmduali/Telegram-Member-Adder

Python Member Adder For Telegram

Language: Python - Size: 24.4 KB - Last synced at: 4 days ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

Mightlaus/CLA-full-adder

A high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.

Language: Verilog - Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

tirtharajsinha/vhdl_codes

vhdl

Language: VHDL - Size: 9.77 KB - Last synced at: 3 months ago - Pushed at: almost 5 years ago - Stars: 4 - Forks: 0

cooljeanius/add_and_multiply

Like my Adder program, except it also multiplies

Language: C - Size: 117 KB - Last synced at: about 1 year ago - Pushed at: almost 13 years ago - Stars: 1 - Forks: 0

lucaszapataEE/BCD_Adder

A project that adds two 4-digit BCD numbers and displays the sum to a 7-segment display.

Size: 5.76 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

muznahsaqiib/3-bit-adder-

Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

vinayak1998/Multiplier-Design

Language: VHDL - Size: 1.16 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

satishkumar1221/Project-Garuda-

Basic VHDL codes. Ask me for more codes and I will publish it in this repository.

Language: VHDL - Size: 41 KB - Last synced at: over 1 year ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

nxbyte/Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Language: Verilog - Size: 2.23 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 91 - Forks: 21

tangopython/Telegram-Adding-Tool

Tool to export members from Telegram Groups and Channels to a CSV file and to add them to Telegram Groups or Channels an DM

Size: 161 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

aliansgp/VHDL_Adders

Different adders code in VHDL and Comparison

Language: C - Size: 1.3 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

IT302/cdl

Chisel Designer's Library

Language: Scala - Size: 20.5 KB - Last synced at: 6 months ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 1

mrtools131/Twitch-ViewBot

Size: 3.91 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 44 - Forks: 0

prosoft4/YouTube-ViewerBot

Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 44 - Forks: 0

SDibla/VHDL-P4_Adder

Pentium 4 adder

Language: VHDL - Size: 86.9 KB - Last synced at: 4 months ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

hbusul/HelloVHDL

Language: VHDL - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

QBlobster/parallel-prefix-adder

A parallel-prefix adder implemented using Ling’s transformation.

Language: SourcePawn - Size: 1.71 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Shakil-RU/Verilog_HDL

"Verilog_HDL" repository contains hardware description language (HDL) code written in Verilog for various digital logic and electronic designs."

Language: Verilog - Size: 87.9 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

FloHofstetter/M9-VLSI-Anwendungen

Summary of projects I did in VLSI desing.

Language: VHDL - Size: 13.7 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

pleontis/ACE203

Projects done in VHDL for course at ECE TUC. Used Xilinx Software either Vivado or ISE.

Language: VHDL - Size: 741 KB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

GokuGhoul/Embd-iverilog

Embedded Systems Lab Work

Language: Verilog - Size: 24.4 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

adityagupta1089/IEEE754-32-bit-adder-subtractor

A C++ program to add two given IEEE754-32 bit floating point numbers.

Language: C++ - Size: 902 KB - Last synced at: almost 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

suoglu/Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

Language: Verilog - Size: 140 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 42 - Forks: 11

s-p-k/shock

A small package to manage logic circuits.

Language: Scheme - Size: 5.66 MB - Last synced at: almost 2 years ago - Pushed at: almost 9 years ago - Stars: 2 - Forks: 0

luckykadam/adder_app 📦

React native app to add two number

Language: Objective-C - Size: 332 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

hosseinfani/digital_odyssey

Materials for the Computer Science course, Digital Design (Logic Circuits)

Language: C++ - Size: 393 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 4

SagarDevAchar/endmodule

Open Source Verilog Modules

Language: Verilog - Size: 52.7 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

newajsharif91/Verilog_HDL_Digital-System-Design

CSE-2112 Digital Syatem Design LAb

Language: Verilog - Size: 6.84 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

neeraj1397/Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

Language: Verilog - Size: 653 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 2

adityagupta1089/EEP206-Verilog

Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.

Language: Verilog - Size: 18.6 KB - Last synced at: almost 2 years ago - Pushed at: about 8 years ago - Stars: 3 - Forks: 2

Radket27/emulator

binary adder

Language: C - Size: 15.6 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language: Verilog - Size: 1.51 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 62 - Forks: 26

uranusx86/AdderNet-on-tensorflow

a implementation of neural network with almost no multiplication with tensorflow 2 (Adder Net)

Language: Python - Size: 8.79 KB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

lil-MoS/AddBot

سورس ربات ادد اجباری برای گروه تلگرام

Language: PHP - Size: 8.79 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 2

IamFlea/AdderCircuitGenerator

This script generates and analyzes prefix tree adders.

Language: Python - Size: 30.3 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 28 - Forks: 4

Daniyar1239/Electronic-dice-and-counter

Electronic dice, two-bit adder and counter made from logic gates in Multimedia Logic software

Size: 349 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

suoglu/FPAM

Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.

Language: Verilog - Size: 27.3 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

daredevilkinng/Telegram-Adder

Cross Platform Telegram Members Scraping and Adding Toolkit

Size: 193 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 4

vincent-camus/carry-cut-back-adder

Carry Cut-Back Adder (CCBA) - An approximate adder circuit with artificially-built false timing paths

Language: VHDL - Size: 6.36 MB - Last synced at: 8 months ago - Pushed at: about 5 years ago - Stars: 6 - Forks: 3

VenciFreeman/SpiceAdders

A 16-bit carry skip adder and an unfinished Kogge-Stone adder.

Language: SourcePawn - Size: 12.1 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

seahore/turing-machine-emulator

一个命令行的图灵机演示模拟器

Language: C++ - Size: 34.2 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 3

scriptographers/CS254-Assignment-5

Assignment 5, Digital Logic Design Lab, Spring 2021, IIT Bombay

Language: VHDL - Size: 709 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

Frankline-Sable/4-Bit-Binary-Adder-and-Subtractor-Wire-Connections

➕➖ Arithmetic operations in most machines are performed in the ALU whereby logic gates and flipflops are combined so that they can subtract, multiply, and divide binary numbers. This circuit only implements the addition part and subtraction on four bit digits

Size: 373 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0