GitHub topics: carry-save-adder
DoniaGameel/Verilog-adders-with-synthesis-using-Oasys
explore different implementations of adders and study their characteristics.
Language: Verilog - Size: 670 KB - Last synced at: 23 days ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 4

Amirreza81/Computer-Architecture
Computer Architecture - Practical Solution with Quartus - Sharif University of Technology
Language: VHDL - Size: 6.95 MB - Last synced at: 4 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Language: Verilog - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 32 - Forks: 6

aliansgp/VHDL_Adders
Different adders code in VHDL and Comparison
Language: C - Size: 1.3 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

FloHofstetter/M9-VLSI-Anwendungen
Summary of projects I did in VLSI desing.
Language: VHDL - Size: 13.7 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

neeraj1397/Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
Language: Verilog - Size: 653 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 6 - Forks: 2
