GitHub / DoniaGameel / Verilog-adders-with-synthesis-using-Oasys
explore different implementations of adders and study their characteristics.
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PURL: pkg:github/DoniaGameel/Verilog-adders-with-synthesis-using-Oasys
Stars: 5
Forks: 4
Open issues: 0
License: None
Language: Verilog
Size: 670 KB
Dependencies parsed at: Pending
Created at: over 2 years ago
Updated at: 5 months ago
Pushed at: over 1 year ago
Last synced at: 4 months ago
Topics: carry-bypass-adder, carry-increment-adder, carry-look-ahead-adder, carry-save-adder, carry-select-adder, carry-skip-adder, floating-point-adder, oasys, ripple-carry-adder