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GitHub topics: carry-skip-adder

mostafa-elgendy22/Adder-Subtractor-Circuits

Parametrized Verilog implementation of different architectures of adder / subtractor circuits.

Language: Verilog - Size: 931 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

DoniaGameel/Verilog-adders-with-synthesis-using-Oasys

explore different implementations of adders and study their characteristics.

Language: Verilog - Size: 670 KB - Last synced at: 17 days ago - Pushed at: 11 months ago - Stars: 2 - Forks: 4

Vedant-02/Verilog-HDL-Lab-Experiments

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

Language: Verilog - Size: 102 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2

Related Keywords
carry-look-ahead-adder 3 carry-select-adder 3 carry-skip-adder 3 ripple-carry-adder 2 carry-bypass-adder 1 carry-increment-adder 1 carry-save-adder 1 floating-point-adder 1 oasys 1 32-bit-alu 1 32-bit-fast-adder 1 4-bit-combinational-adder 1 4-bit-comparator 1 4-bit-parallel-adder 1 adder-subtractor 1 barrel-shifter 1 bcd-adder 1 bcd-subtractor 1 bcd-to-7-segment 1 binary-multiplier 1 binary-to-gray 1 full-adder 1 hacktoberfest 1 hacktoberfest2022 1 priority-encoder 1 verilog 1