GitHub topics: bcd-to-7-segment
Mehedi-86/Logisim_Projects
This repository includes Logisim Evolution circuits for a 3-Bit Down Counter, BCD to Excess-3 Converter, BCD to Hex Display, 4-Bit Comparator, and Cache Memory, covering sequential logic, number conversions, and memory design. 🚀
Size: 769 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
gmostofabd/8051-7Segment
📦 This repository demonstrates how to interface a single-digit Seven-Segment Display (SSD) with the 8051 microcontroller using assembly language. A common cathode SSD is utilized in this project, with all necessary files provided, including assembly code, Proteus simulation files, HEX files, and photos from testing. Later we included 2 digits exam
Language: HTML - Size: 360 KB - Last synced at: 3 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
henryhale/7-segment-display-decoder
📟 A BCD to seven segment display decoder implementation
Language: JavaScript - Size: 120 KB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1
ATOMIC09/Ten_bit_binary_to_3_digit_7_segment
What happens if I push Quartus Prime to GitHub?
Language: VHDL - Size: 5.06 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Vedant-02/Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Language: Verilog - Size: 102 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2
