GitHub / Vedant-02 / Verilog-HDL-Lab-Experiments

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

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Topics: 32-bit-alu, 32-bit-fast-adder, 4-bit-combinational-adder, 4-bit-comparator, 4-bit-parallel-adder, adder-subtractor, barrel-shifter, bcd-adder, bcd-subtractor, bcd-to-7-segment, binary-multiplier, binary-to-gray, carry-look-ahead-adder, carry-select-adder, carry-skip-adder, full-adder, hacktoberfest, hacktoberfest2022, priority-encoder, verilog

• Files
• Readme
• Dependencies