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GitHub topics: 4-bit-combinational-adder

joeymaillette04/VHDL

VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design

Language: VHDL - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Vedant-02/Verilog-HDL-Lab-Experiments

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

Language: Verilog - Size: 102 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2

Related Keywords
4-bit-combinational-adder 2 full-adder 2 verilog 1 priority-encoder 1 hacktoberfest2022 1 hacktoberfest 1 carry-skip-adder 1 carry-select-adder 1 carry-look-ahead-adder 1 binary-to-gray 1 binary-multiplier 1 bcd-to-7-segment 1 bcd-subtractor 1 bcd-adder 1 barrel-shifter 1 adder-subtractor 1 4-bit-parallel-adder 1 4-bit-comparator 1 32-bit-fast-adder 1 32-bit-alu 1 vhdl 1 half-adder 1 digital-design 1 combinational-logic 1 binary-logic 1