GitHub topics: vhdl

Repositories

wumphlett/COMP-4300

Auburn COMP 4300 Assignments

Language: VHDL - Size: 2.37 MB - Last synced at: about 7 hours ago - Pushed at: about 7 hours ago - Stars: 1 - Forks: 2

akaeba/eSpiMasterBfm

Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master

Language: VHDL - Size: 288 KB - Last synced at: about 16 hours ago - Pushed at: about 16 hours ago - Stars: 8 - Forks: 4

OTANK10/Random-Number-Generation

Comprehensive Random Number Generator implementation featuring both Pseudo-Random Number Generator (PRNG) using Linear Feedback Shift Registers and True Random Number Generator (TRNG) using Ring Oscillators

Language: VHDL - Size: 6.84 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

LuisMLopez-dev/Double-Dabble-Algorithm

This is a VHDL code for converting a binary number to a BCD (binary-coded decimal) number using the Double Dabble Algorithm.

Language: VHDL - Size: 10.7 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

Krasnomakov/FPGA

This repository contains Verilog/C examples with Tang Nano (4K/9K/20K) and Zybo Z7

Language: F# - Size: 33.3 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 2 - Forks: 1

slaclab/surf

A huge VHDL library for FPGA and digital ASIC development

Language: VHDL - Size: 171 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 390 - Forks: 72

VHDL/PoC Fork of VLSI-EDA/PoC

IP Core Library - Published and maintained by the Open Source VHDL Group

Language: VHDL - Size: 11.1 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 14 - Forks: 1

siliconcompiler/siliconcompiler

Modular hardware build system

Language: Python - Size: 336 MB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 1,032 - Forks: 106

alikhaled14589653/DE2-MissileCommand

Missile Command Arcade synthesized on an Altera DE2-35 Dev Board.

Language: Verilog - Size: 246 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

shishir-dey/vhdl-samples

Contains VHDL netlists of basic digital circuits

Language: VHDL - Size: 6.26 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 3 - Forks: 0

ghdl/ghdl

VHDL 2008/93/87 simulator

Language: VHDL - Size: 79.2 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 2,574 - Forks: 386

logisim-evolution/logisim-evolution

Digital logic design tool and simulator

Language: Java - Size: 109 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 5,855 - Forks: 739

Chufretalas/N_size_ALU

A very simple variable size ALU made in VHDL

Language: VHDL - Size: 14.6 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

s-grundner/LVA-VHDL-PR

Hardwaredesign mit VHDL - Praktikum

Language: VHDL - Size: 84 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

yunusdolfin/yesergun.fpga.dev

All about FPGA...

Language: Tcl - Size: 2.25 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 3 - Forks: 0

ElecGeek/PulsesDigital

Fun project to produce (only) pulses as the MultiSignalGene do, with FPGA or ASIC

Language: VHDL - Size: 36.1 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

akhil-b-26/8bit-ALU-vhdl

The project involves designing an 8-bit Arithmetic Logic Unit (ALU) using Verilog. The ALU performs eight different operations based on a 3-bit opcode, making it a fundamental component in digital circuits and processors. The implementation includes both the ALU module and a testbench to verify its functionality.

Language: VHDL - Size: 114 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 19.8 MB - Last synced at: 1 day ago - Pushed at: 3 days ago - Stars: 1,509 - Forks: 162

olofk/fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

Language: Python - Size: 2.49 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,300 - Forks: 260

hdl-modules/hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Language: VHDL - Size: 3.46 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 171 - Forks: 31

Ocha-byte/VHDL

Personal VHDL projects

Language: VHDL - Size: 381 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 1

owocomm-0/fpga-fft

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

Language: VHDL - Size: 2.1 MB - Last synced at: about 7 hours ago - Pushed at: over 4 years ago - Stars: 114 - Forks: 23

tmeissner/formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

Language: VHDL - Size: 205 KB - Last synced at: 2 days ago - Pushed at: over 1 year ago - Stars: 42 - Forks: 7

HEP-SoC/SoCMake

CMake based hardware build system

Language: CMake - Size: 6.07 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 27 - Forks: 3

CTipton27/FPGA_Pong

Language: VHDL - Size: 21.5 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.25 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 26 - Forks: 5

nickg/nvc

VHDL compiler and simulator

Language: C - Size: 25.6 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 705 - Forks: 90

stnolting/neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Language: VHDL - Size: 226 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,786 - Forks: 267

stnolting/neorv32-riscof

✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

Language: Python - Size: 15.6 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 34 - Forks: 8

stnolting/neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Language: VHDL - Size: 857 KB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 79 - Forks: 26

MatthieuMichon/vivado-vhdl-time-const-calc

Xilinx Vivado issue with VHDL time type handling

Language: Tcl - Size: 34.2 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

jpt13653903/tree-sitter-vhdl

A VHDL parser for syntax highlighting.

Language: VHDL - Size: 17.6 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 15 - Forks: 2

usman1515/vga_framebuffer

VGA controller with a BRAM framebuffer for the Basys3 and Nexys A7 FPGA Boards

Language: VHDL - Size: 1.4 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

alpyen/fpga-mediaplayer

HDL, Hardware & Software Development project to playback a video with sound and learn while doing so.

Language: VHDL - Size: 15.2 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

saadelahii/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1.01 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

Lolitka123/MicroLab

Particle simulation software built in processing which demonstrates complex emergent behaviour and forms life-like structures

Language: Processing - Size: 16.6 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 1

JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Language: VHDL - Size: 76.1 MB - Last synced at: 6 days ago - Pushed at: 7 days ago - Stars: 658 - Forks: 51

house-of-abbey/scratch_vhdl

The purpose of "Scratch VHDL" is to make reprogrammable logic design into child's play. Sounds ambitious.

Language: TypeScript - Size: 101 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 8 - Forks: 1

Kampi/VHDL

Some VHDL projects, created with and for my ZYBO.

Language: VHDL - Size: 79.6 MB - Last synced at: 3 days ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

SpinalHDL/SpinalHDL

Scala based HDL

Language: Scala - Size: 81.3 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 1,800 - Forks: 348

ANSSI-FR/IPECC

A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration

Language: VHDL - Size: 33.3 MB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 38 - Forks: 9

raczben/fliplot

HTML & Js based VCD viewer

Language: JavaScript - Size: 776 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 60 - Forks: 17

cocotb/cocotb

cocotb: Python-based chip (RTL) verification

Language: Python - Size: 8.76 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 2,003 - Forks: 557

MarianaGranados-09/DigitalSystems

Digital Systems course material 2025-1.

Language: VHDL - Size: 137 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

OSVVM/OsvvmLibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

Size: 242 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 64 - Forks: 23

OpenEDF/verilog-basic

learn the combinational and sequential logic circuit.

Language: SystemVerilog - Size: 24.3 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 15 - Forks: 1

jofrfu/HAW-V

Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg

Language: VHDL - Size: 31.9 MB - Last synced at: 10 days ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 3

AlvaroDavi5/Programacao_e_Desenvolvimento

Language: JavaScript - Size: 306 MB - Last synced at: 10 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Language: VHDL - Size: 25 MB - Last synced at: 3 days ago - Pushed at: about 1 month ago - Stars: 202 - Forks: 39

edaa-org/pyEDAA.OSVVM

Parsing and Converting OSVVM Specific Data Formats.

Language: Python - Size: 5.59 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 3 - Forks: 0

ThalesGroup/udp-offload-engine

UDP-IP stack accelerator and is able to send and receive data through Ethernet link

Language: VHDL - Size: 1.54 MB - Last synced at: 8 days ago - Pushed at: 4 months ago - Stars: 24 - Forks: 5

hVHDL/hVHDL_floating_point

high level VHDL floating point library for synthesis in fpga

Language: VHDL - Size: 206 KB - Last synced at: 6 days ago - Pushed at: 4 months ago - Stars: 17 - Forks: 2

richjyoung/vscode-modern-vhdl

Modern VSCode VHDL Support

Language: TypeScript - Size: 188 KB - Last synced at: 11 days ago - Pushed at: about 3 years ago - Stars: 31 - Forks: 11

leticia-pontes/vhdl

Códigos e imagens de simulação de circuitos lógicos desenvolvidos em aula

Language: VHDL - Size: 544 KB - Last synced at: 11 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

VHDL/pyVHDLModel

An abstract language model of VHDL written in Python.

Language: Python - Size: 6.95 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 54 - Forks: 12

Nic30/hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Language: C++ - Size: 14.4 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 298 - Forks: 73

Nic30/hwtLib

hardware library for hwt (= ipcore repo)

Language: Python - Size: 6.37 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 38 - Forks: 7

Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Language: Python - Size: 19.3 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 212 - Forks: 28

Nic30/hdlConvertorAst

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Language: Python - Size: 781 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 36 - Forks: 9

OSVVM/OSVVM

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Language: VHDL - Size: 18.9 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 242 - Forks: 69

XedaHQ/xeda

Cross EDA Abstraction and Automation

Language: Python - Size: 128 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 39 - Forks: 5

S2Sofficial/vhdl

This is my FPGA VHDL Programming Journey.

Language: VHDL - Size: 23.5 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 1 - Forks: 1

markus-k/rv32-soc

A simple RISC-V SoC based on picorv32

Language: VHDL - Size: 26.4 KB - Last synced at: 1 day ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0

PyFPGA/HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Language: Python - Size: 5.15 MB - Last synced at: 13 days ago - Pushed at: 4 months ago - Stars: 25 - Forks: 2

chaseruskin/verb

An approachable testing framework for digital hardware

Language: Python - Size: 1.99 MB - Last synced at: 3 days ago - Pushed at: 28 days ago - Stars: 4 - Forks: 0

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.05 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 695 - Forks: 203

MJoergen/C64MEGA65 Fork of sy2002/MiSTer2MEGA65

Commodore 64 core for the MEGA65 based on the MiSTer FPGA C64 core

Language: VHDL - Size: 48 MB - Last synced at: 6 days ago - Pushed at: about 2 months ago - Stars: 36 - Forks: 5

Related Keywords

vhdl 2,417 fpga 864 verilog 309 vivado 162 vhdl-code 154 xilinx 148 hardware 122 cpu 109 c 104 hdl 101 python 100 vhdl-examples 93 systemverilog 93 quartus 90 computer-architecture 83 rtl 71 simulation 71 mips 71 processor 67 modelsim 66 fpga-programming 58 ghdl 57 digital-design 50 xilinx-fpga 49 risc-v 48 altera 47 xilinx-vivado 46 hardware-designs 42 asic 42 cpp 42 mips-architecture 39 assembly 39 microprocessor 39 testbench 38 vga 38 verification 36 embedded-systems 36 vhdl-modules 35 matlab 34 fsm 34 uart 34 synthesis 33 vhdl-coursework 33 alu 32 electronics 32 hardware-description-language 32 xilinx-ise 31 polimi 31 java 29 digital 29 vlsi 28 quartus-prime 28 soc 28 game 28 assembler 27 risc 27 fpga-soc 27 riscv 26 vhdl-testbench 26 dsp 25 image-processing 25 tcl 24 finite-state-machine 23 design 22 basys3 22 digital-systems 22 embedded 21 fpga-board 21 verilog-hdl 21 eda 21 verilator 20 digital-logic 19 architecture 19 cocotb 19 digital-electronics 19 yosys 19 zynq 18 cpld 18 digital-signal-processing 18 digital-logic-design 18 altera-fpga 17 mips-assembly 17 intel 17 open-source 17 linux 17 ise 17 logic-gates 16 python3 16 vga-controller 16 processor-architecture 16 quartus2 16 spi 16 digital-circuits 16 ethernet 16 counter 15 microcontroller 15 gtkwave 15 arm 15 logic 15 adder 15