azonenberg/antikernel

The Antikernel operating system project

Language: Verilog - Size: 8.67 MB - Last synced at: 1 day ago - Pushed at: almost 5 years ago - Stars: 119 - Forks: 10

Choaib-ELMADI/risc-v-on-de1-soc-fpga

A simplified RISC-V processor implemented in Verilog and deployed on the DE-1 SoC FPGA board.

Language: Verilog - Size: 24.3 MB - Last synced at: 7 days ago - Pushed at: 8 days ago - Stars: 4 - Forks: 2

strath-sdr/rfsoc_radio

PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.

Language: VHDL - Size: 55.4 MB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 35 - Forks: 11

trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Language: SystemVerilog - Size: 20.4 MB - Last synced at: 1 day ago - Pushed at: almost 5 years ago - Stars: 598 - Forks: 102

HRL-Laboratories/spinqick

An open-source control library for electrostatically confined spin-qubits developed by HRL Quantum and based on the Quantum Instrumentation Control Kit (QICK).

Language: Python - Size: 272 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 6 - Forks: 0

lnis-uofu/OpenFPGA

An Open-source FPGA IP Generator

Language: Verilog - Size: 88.9 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 893 - Forks: 170

dpretet/axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

Language: SystemVerilog - Size: 438 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 142 - Forks: 27

Choaib-ELMADI/working-with-fpga-and-vhdl

A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.

Language: VHDL - Size: 12.4 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 4 - Forks: 0

Choaib-ELMADI/working-with-fpga-and-mips

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.

Language: Verilog - Size: 11.2 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 4 - Forks: 0

ryuz/jelly

Original FPGA platform

Language: Verilog - Size: 18.4 MB - Last synced at: about 4 hours ago - Pushed at: about 5 hours ago - Stars: 62 - Forks: 16

EngineerMichael/-Robotic-Arm---Haddington-Dynamics-Robotics-Engineering-

⎔ Automation in 3D-Printed Robotics in C & JS (Revising Custom JavaScript Source Code Files)

Language: JavaScript - Size: 4 MB - Last synced at: 13 days ago - Pushed at: about 2 months ago - Stars: 6 - Forks: 0

strath-sdr/rfsoc_qpsk

PYNQ example of using the RFSoC as a QPSK transceiver.

Language: VHDL - Size: 65 MB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 100 - Forks: 47

j-schacht/xilinx_zcu102_trustzone_demo

Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone

Language: C - Size: 69 MB - Last synced at: 5 days ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 2

dawsonjon/chips_v

RISC-V System on Chip Builder

Language: Verilog - Size: 1.07 MB - Last synced at: 21 days ago - Pushed at: over 4 years ago - Stars: 12 - Forks: 2

ultraembedded/riscv_soc

Basic RISC-V Test SoC

Language: Verilog - Size: 6.1 MB - Last synced at: 15 days ago - Pushed at: about 6 years ago - Stars: 119 - Forks: 31

tommythorn/yarvi

Yet Another RISC-V Implementation

Language: Roff - Size: 2.82 MB - Last synced at: 3 days ago - Pushed at: 7 months ago - Stars: 91 - Forks: 24

JunningWu/Learning-NVDLA-Notes

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Size: 4 MB - Last synced at: 21 days ago - Pushed at: over 6 years ago - Stars: 225 - Forks: 66

robseb/HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Language: Verilog - Size: 11 MB - Last synced at: 8 days ago - Pushed at: almost 4 years ago - Stars: 37 - Forks: 13

Obijuan/Z80-FPGA

Z80 CPU for OpenFPGAs, with Icestudio

Language: Assembly - Size: 4.45 MB - Last synced at: 15 days ago - Pushed at: 11 months ago - Stars: 77 - Forks: 18

arm-university/Modern-System-on-Chip-Design-on-Arm

A textbook on system on chip design using Arm Cortex-A

Size: 40.8 MB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 25 - Forks: 6

micro-FPGA/engine-V

SoftCPU/SoC engine-V

Language: Verilog - Size: 14.6 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 54 - Forks: 7

strath-sdr/rfsoc_sam

RFSoC Spectrum Analyser Module on PYNQ.

Language: VHDL - Size: 133 MB - Last synced at: 7 days ago - Pushed at: 10 months ago - Stars: 76 - Forks: 23

tommythorn/yari

YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.

Language: C - Size: 30.8 MB - Last synced at: 3 days ago - Pushed at: 5 months ago - Stars: 45 - Forks: 9

trivialmips/TrivialMIPS

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

Language: SystemVerilog - Size: 84.3 MB - Last synced at: 1 day ago - Pushed at: almost 6 years ago - Stars: 106 - Forks: 35

fpw/SoCDP8

A SoC implementation of a PDP-8/I for the PiDP-8/I console

Language: C - Size: 37 MB - Last synced at: 17 days ago - Pushed at: about 1 year ago - Stars: 29 - Forks: 3

ultraembedded/fpga_test_soc

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

Language: C - Size: 1.11 MB - Last synced at: 15 days ago - Pushed at: about 5 years ago - Stars: 31 - Forks: 11

Jjateen/RISC-V-SoC

This repository contains a custom RISC-V-based System-on-Chip (SoC) implemented on the Tang Nano 9K FPGA. It utilizes PicoRV32 and FemtoRV32 cores along with UART communication and runs a dedicated firmware.

Language: F# - Size: 1.47 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Kampi/OV7670

FPGA interface and driver for an OV7670 camera sensor.

Language: VHDL - Size: 31.3 KB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

TahirZia-1/UART-Transmitter-and-Receiver

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

TahirZia-1/Digital-Clock-Verilog

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Language: Tcl - Size: 166 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/getting-started-with-vhdl

Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.

Language: VHDL - Size: 38.5 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 6 - Forks: 0

calvinee/FPGA-Technology-Weekly

分享FPGA相关的新闻，好技术文章，博客和项目，帮助大家入门FPGA系统开发，和工作创业交流。Share FPGA-related news, quality technical articles, blogs, and projects to help everyone get started with FPGA system development and exchange ideas on work and entrepreneurship.

Size: 14.6 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Language: Verilog - Size: 8.73 MB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 90 - Forks: 21

tommythorn/fpgammix

Partial implementation of Knuth's MMIX processor (FPGA softcore)

Language: C - Size: 475 KB - Last synced at: 3 days ago - Pushed at: about 5 years ago - Stars: 51 - Forks: 9

dan-lara/FPGA-Ultrasonic-2D-Radar

Language: C - Size: 21.5 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

mikeroyal/FPGA-Guide

FPGA Guide

Language: Verilog - Size: 25.4 KB - Last synced at: 22 days ago - Pushed at: over 3 years ago - Stars: 12 - Forks: 2

QuorumComp/hc800

HC800 Home Computer core

Language: Verilog - Size: 1.37 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 4 - Forks: 0

10x-Engineers/Infinite-ISP_LinuxCameraStack

Extending Linux support to enable Infinite-ISP on FPGA for the development of a libcamera-based camera application stack.

Language: C++ - Size: 8.73 MB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 2 - Forks: 2

alinja/alpus_wb

VHDL implementation of Pipelined Wishbone B4 interconnect

Language: VHDL - Size: 13.7 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

Choaib-ELMADI/fpga-programming-for-beginners

A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.

Language: Tcl - Size: 30.4 MB - Last synced at: about 1 month ago - Pushed at: 8 months ago - Stars: 11 - Forks: 1

somdipdey/MAT-CNN-SOPC

MAT-CNN-SOPC: Motionless Analysis of Traffic Using Convolutional Neural Networks on System-On-a-Programmable-Chip

Language: HTML - Size: 16.9 MB - Last synced at: 16 days ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 3

ZipCPU/openarty

An Open Source configuration of the Arty platform

Language: Verilog - Size: 14.2 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 122 - Forks: 24

splAcharya/DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Size: 71.2 MB - Last synced at: 5 months ago - Pushed at: over 4 years ago - Stars: 18 - Forks: 4

Insper/Embarcados-Avancados

SoC and Embedded Linux

Language: JavaScript - Size: 81.3 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 11

habibaouinti/NPU_X_Interface

Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.

Language: SystemVerilog - Size: 92.8 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

ASP-SoC/ASP-SoC.github.io

Audio Signal Processing SoC Project Website

Language: HTML - Size: 3.96 MB - Last synced at: 8 months ago - Pushed at: about 8 years ago - Stars: 6 - Forks: 1

RISMicroDevices/RMM4NC30F2X 📦

Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022

Language: VHDL - Size: 31.3 MB - Last synced at: 9 months ago - Pushed at: over 2 years ago - Stars: 9 - Forks: 1

BLangOS/VexRiscV_with_HW-GDB_Server

VexRiscV system with GDB-Server in Hardware

Language: VHDL - Size: 346 KB - Last synced at: 12 days ago - Pushed at: almost 2 years ago - Stars: 20 - Forks: 4

marco-pag/fred-linux

Experimental implementation of FRED for Linux.

Language: C - Size: 246 KB - Last synced at: 10 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 4

anchaides/docker-arm-gnuabihf-de1-soc

Helps with Cross compilation for arm-gnueabihf-gcc linux compilation for the HPS found in cyclone V subsystems on DE1-SOC boards.

Language: Dockerfile - Size: 14.6 KB - Last synced at: 10 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

3-o-3/cod5

Public Domain (⊄) Computer on FPGA

Language: C - Size: 87.5 MB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Simple-Nios2-Project

Designing a simple processor system on FPGA. This is demo project to test FPGA DE10-Standard and develop a simpe Nios2 app.

Language: Verilog - Size: 1.37 MB - Last synced at: 11 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Project-Nios2-DMA-Accelerator

Develop DMA acceleration of the system that performs linear computing functions, Y = AX + B, large amounts of data.

Size: 18.6 KB - Last synced at: 11 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

ASP-SoC/ASP-SoC

Audio Signal Processing SoC

Language: VHDL - Size: 33.9 MB - Last synced at: 8 months ago - Pushed at: about 7 years ago - Stars: 17 - Forks: 8

CNES/LoCod

An open-source hw/sw co-design framework for heterogeneous chips

Size: 3.91 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

icebreaker-fpga/icetwang

An iCEBreaker-Bitsy based 1D game system, using intelligent LED strings and springs as controllers.

Language: Rust - Size: 3.7 MB - Last synced at: 12 months ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 1

dpretet/friscv

RISCV CPU implementation in SystemVerilog

Language: Coq - Size: 4.1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 15 - Forks: 4

cyber-murmel/nmigen-wishbone-examples

A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91

Language: Python - Size: 298 KB - Last synced at: 12 months ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

ikwzm/FPGA-SoC-U-Boot-ZYBO-Z7

U-Boot image for ZYBO-Z7

Language: Shell - Size: 2.96 MB - Last synced at: 4 days ago - Pushed at: almost 7 years ago - Stars: 6 - Forks: 2

romanmashta/mini186_SoC

Language: Verilog - Size: 310 KB - Last synced at: 12 months ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 2

Qyt0109/My-own-RISC-V-ISA-based-CPU-on-FPGAs

RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.

Language: Verilog - Size: 7.18 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

mnemocron/my-discrete-fpga

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

Language: VHDL - Size: 9.57 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

esa-tu-darmstadt/tapasco

The Task Parallel System Composer (TaPaSCo)

Language: Verilog - Size: 104 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 94 - Forks: 24

ikwzm/FPGA-SoC-U-Boot-DE10-Nano

U-Boot image for DE10-Nano

Language: Shell - Size: 251 KB - Last synced at: 4 days ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 2

Johnritaa/SmartFusion2-UART-demo

demo program for SmartFusion2 FPGA SOC

Size: 12.3 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

nobotro/fpga_riscv_cpu

fpga verilog risc-v rv32i cpu

Language: Verilog - Size: 97.3 MB - Last synced at: 11 months ago - Pushed at: about 2 years ago - Stars: 8 - Forks: 2

timvideos/HDMI2USB-litex-firmware

A version of the HDMI2USB firmware based around LiteX tools produced by @Enjoy-Digital (based on misoc+migen created by @M-Labs)

Language: Python - Size: 8.23 MB - Last synced at: about 1 year ago - Pushed at: about 5 years ago - Stars: 139 - Forks: 74

pronoym99/AHWR-Interlock

Language: VHDL - Size: 14.6 MB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

HawkPhantom/FPGA-Sorting

This Repo includes C++ codes, Verilog IPs and Complete Zynq applications of sorting algorithms.

Language: C++ - Size: 1.03 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

open-photonics/lightning

[SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference

Language: Verilog - Size: 14 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

jingpu/Halide-HLS

HLS branch of Halide

Language: C++ - Size: 239 MB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 74 - Forks: 21

raetro/sdk-docker-fpga

Intel Quartus Prime Synthesis Engine for Docker

Language: Dockerfile - Size: 847 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 31 - Forks: 7

TotoroTron/Pong

Arcade pong on a 32x32 LED matrix.

Language: VHDL - Size: 4.55 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

pokitoz/DE0_SoC_altera_config

Language: C - Size: 133 KB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 1

siorpaes/SimpleSoC

Very simple Cortex-M1 SoC design based on ARM DesignStart

Language: C - Size: 206 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 2

leastrobino/acoustic-levitation

Acoustic levitation on SoC FPGA (DE0-Nano-SoC). Notice: this repository has moved to GitLab. All issues and pull requests should be created there.

Language: VHDL - Size: 190 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 18 - Forks: 4

monistode/ISA_stack

An implementation of the RISC stack ISA spec from ISA-docs

Language: SystemVerilog - Size: 19.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

mukullokhande99/fifo_hardware_fpga

FIFO implemented on FPGA Spartan 6

Language: Rich Text Format - Size: 21.4 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 1

aidanrhind/License_Plate_Detection_yolov4_KV260

Custom YoloV4 Darknet/Tensorflow model for license plate detection on the AMD-Xilinx Kria KV260 Vision-AI starter Kit. Utilize transfer learning to create your own custom object detecion model on a custom dataset, quantize and compile in Vitis-AI for easy deployment and evaluation on FPGA.

Language: Shell - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

lazuardinfl/Tic-tac-toe-FPGA

Tic-Tac-Toe with SoC FPGA

Language: VHDL - Size: 25.3 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

jorenvandeweyer/soclab_project

Language: Verilog - Size: 4.81 MB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 0

vrstanchev/gnu-fpga-exersises

VHDL fpga exersises with Free/FOSS/Libre tools

Language: VHDL - Size: 17.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

esantosjr/FPGA-Function-Acceleration

Accelerating a simple function using an IP Block in the FPGA.

Language: Tcl - Size: 2.13 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hipersys-team/lightning

[SIGCOMM 2023] Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference

Language: Verilog - Size: 14 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 28 - Forks: 3

jiadong5/ECE385_SP23_ZJUI

Final Project third-perspective-shooting video game PokeHead and some other lab codes and design of ECE385 Digital Systems Laboratory

Language: C - Size: 68.7 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

ngrabbs/arm_projects

ARM single cycle processor on nandland.com go-board

Language: SystemVerilog - Size: 20.9 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

gergo-papp/SystemOnChip-ImageProcessing-myRIO

Image Processing Algorithms on System-on-Chip FPGA Devices using a myRIO as hardware and LabVIEW as software

Language: LabVIEW - Size: 6.27 MB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 3

feddischson/de0_led_example

A very small example project for the Terasic DE0 SOC board.

Language: Makefile - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 3

feddischson/de0_hps_example

Examples for the Terasic DE0-nano-SOC board

Language: Makefile - Size: 51.8 KB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

timvideos/qemu-litex Fork of mithro/qemu-litex

Language: C - Size: 119 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 2

DiegoRosales/Zybo_Sampler

Audio Sampler for Zybo

Language: C - Size: 43.1 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 1

Domipheus/ArtyS7-RPU-SoC

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

Language: VHDL - Size: 18.8 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 33 - Forks: 6

yilmaz0734/FPGATictactoegame

In this project, we implemented a different kind of a tic tac toe board game that is played on an FPGA board using its push buttons. We used Verilog HDL to code the project and implemented a VGA interface for visualization.

Language: Verilog - Size: 22.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hex-five/multizone-fpga Fork of sifive/freedom

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its MultiZone Security Trusted Execution Environment and MultiZone Security Trusted Firmware. The X300 is an enhanced secure version of the - now archived - SiFive's Freedom E300 Platform built around the RISC-V Rocket chip originally developed at U.C. Berkeley.

Language: Scala - Size: 212 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 5

AhmedAbdelaal2001/Advanced-Encryption-Standard

A full hardware implementation of the AES using Verilog, supporting SPI communication between all modules.

Language: Verilog - Size: 22.5 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

avlad98/Hybrid_CPU_FPGA_DisertationProject

[Disertation Project] Hybrid CPU and FPGA image processing on a Zybo Z7-10 SoC (Zynq7000) from Xilinx

Language: VHDL - Size: 267 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

fmhess/fmh_gpib_core

GPIB IEEE 488.1 core

Language: VHDL - Size: 511 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 18 - Forks: 8

peacekeeper228/labHPS

working with HPS

Language: C - Size: 17.6 KB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 10 - Forks: 0

splinedrive/lets_build_a_compiler_for_riscv

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

Language: C - Size: 2.65 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 21 - Forks: 4

Goshik92/multicore-nios

Matrix multiplication on multiple Nios II cores

Language: C - Size: 399 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 11 - Forks: 6