GitHub topics: verilog-project | Ecosyste.ms: Repos

K4V4NH/Basic-Verilog-Codes

Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.

Language: Verilog - Size: 18.6 KB - Last synced at: about 18 hours ago - Pushed at: about 19 hours ago - Stars: 1 - Forks: 0

Joshvareba11/model-memory-calculator

📊 Estimate memory usage for GGUF models in your browser, using local files or remote URLs, with no server needed and seamless performance.

Language: HTML - Size: 1.31 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

tejasbhujade1603/RTL_GDS_RV_SoC_Week_3

🔍 Conduct an in-depth review of Week 3 tasks for the VSD RV SoC Tapeout Program, showcasing key findings and insights.

Size: 2.59 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Language: VHDL - Size: 25 MB - Last synced at: 11 days ago - Pushed at: 6 months ago - Stars: 217 - Forks: 41

Shihara1020/CO224-Building_Processor

CO224 Computer Architecture Labs - 8-bit Single-Cycle Processor Implementation .

Language: Verilog - Size: 10.2 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

rajdeep13-coder/Verilog-Basic-Projects

This repository is a collection of basic to intermediate Verilog projects, designed to strengthen digital design fundamentals and prepare for VLSI design and FPGA/ASIC flows. Each module is written in Verilog HDL with a testbench, and are simulated using tools like online IDEs like EDA Playground.

Language: Verilog - Size: 10.7 KB - Last synced at: 28 days ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

capopaul/Public-Verilog-Design-Flow-And-Environment

Provide a basic structure to starts a Verilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)

Language: Verilog - Size: 9.77 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

pickle-lotus0976/EDA

This repository serves as a personal portfolio and learning log for various FPGA designs. Each top-level folder contains a distinct, self-contained Vivado project. The focus is on creating clean, reproducible, and well-documented hardware designs.

Language: C - Size: 68.4 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

SACHINUR17/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: SystemVerilog - Size: 8.76 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 3 - Forks: 0

Pratim-Senapati/qflow-projects

A complete setup for Qflow, an open-source digital VLSI design flow. This repo provides pre-configured example projects, automated installation scripts, and step-by-step instructions to synthesize, place, and route Verilog designs into GDSII layouts. Supports both running example designs and using your own Verilog.

Language: Python - Size: 9.36 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

mohit-yadav-21/ES204_Final_Project

Final project for Digital Systems, IITGN Spring '25

Language: Verilog - Size: 723 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 1

ErickMaRi/HDL-Bitnet-1.58

Transformer Bitnet en Verilog

Language: Verilog - Size: 4 MB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 2

underthenightsky/7_Segment_Display

This project implements and simulates a 7-segment display decoder in Verilog. The decoder takes a 4-bit binary input (representing values 0–15) and generates the corresponding 7-bit output pattern to drive a 7-segment display.

Language: Verilog - Size: 2.93 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

theteamonk/router1x3

Router 1x3 Design and Verification in Verilog

Language: Verilog - Size: 429 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

Language: Verilog - Size: 12.6 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 4 - Forks: 2

galihru/logicsim

The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin

Language: JavaScript - Size: 423 KB - Last synced at: 19 days ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

Karan-nevage/Memory-UVM-Verification

This project provides a comprehensive verification framework for a synchronous single-port RAM module implemented in Verilog. The memory module is configurable with parameters for data width, memory depth, and address width. It operates synchronously with a clock signal and uses a valid-ready handshake protocol to control read and write operations.

Language: SystemVerilog - Size: 85.9 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

ADHIL48/Verilog-HDL-Project-Hub

This repository contains Verilog HDL projects covering arithmetic units, memory blocks, FSMs, and protocols. It’s perfect for VLSI and FPGA learners to practice and understand digital design through synthesizable modules.

Language: Verilog - Size: 14.9 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Language: Verilog - Size: 8.73 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 105 - Forks: 26

Sakshipandey04/4-Bit-ALU

Four(4)- bit Arithmetic Logic Unit (ALU) implemented in Verilog with Vivado simulation

Language: Verilog - Size: 226 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

marianoterra/Verilog-MathFunctions

Implement a Verilog digital system for approximating exp(x), sin(x), cos(x), and ln(1+x) using Taylor/Maclaurin series. Ideal for FPGA and simulation. 🚀💻

Language: Verilog - Size: 44.9 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Raghad-alju/fsm-sequence-detector

Implement a 3-bit sequence detector for `110` using a Mealy FSM in Cadence Virtuoso. Built with TSPC D flip-flops for optimal performance. 🛠️💻

Size: 808 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

jElhamm/Verilog-HDL-Codes-Collection

"Repository containing a collection of Verilog code modules and test bench for digital design projects. "

Language: Verilog - Size: 387 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

nimanaqavi/Verilog-MathFunctions

A Verilog-based system for approximating mathematical functions (exp, sin, cos, ln) using Taylor/Maclaurin series, suitable for FPGA implementation and simulation.

Language: Verilog - Size: 66.4 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

Vaibhav-Gunthe/Verilog-Projects

A collection of Verilog-based digital design projects, from basic gates to complex modules like ALUs, FSMs, and memory units. Ideal for learning RTL design and synthesis.

Language: Verilog - Size: 2.15 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 4 - Forks: 0

ADHIL48/Verilog-HDLBits-Solutions

This is a repository containing solutions to the problem statements given in Verilog HDL Bits website.

Language: Verilog - Size: 0 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

Language: Verilog - Size: 126 KB - Last synced at: 4 months ago - Pushed at: almost 2 years ago - Stars: 132 - Forks: 23

sakethakella/FFT_DIT_8point

8-point FFT calculator

Language: Verilog - Size: 4.88 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

sushi0706/verilog-mini-projects

Verilog Mini Projects

Language: Verilog - Size: 49.8 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 1

Madhu-Krishnan-A-P/4bitadder

Verilog implementations of a 4-bit adder using behavioral, dataflow, and structural modeling styles, along with corresponding testbenches and block diagrams. This project demonstrates the design and simulation of digital adders as part of an academic lab experiment.

Language: Verilog - Size: 1.26 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

nesterovmaxim31/Simpson-s-rule-Verilog

Построение синхронного цифрового автомата для реализации метода Симсона с дальнейшей загрузкой на ПЛИС Artix-7 xс7a100tcsg324-1I

Language: Verilog - Size: 1.36 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

NikhilMukraj/spiking-neural-networks-hardware

An FPGA design for simulating biological neurons

Language: SystemVerilog - Size: 437 KB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 14 - Forks: 0

adibis/DDR2_Controller

DDR2 memory controller written in Verilog

Language: Verilog - Size: 116 KB - Last synced at: 5 months ago - Pushed at: over 13 years ago - Stars: 78 - Forks: 32

vishnuvarshini26/verilog-project

A beginner-level project that implements a 4-bit Arithmetic Logic Unit (ALU) supporting basic operations like ADD, SUB, AND, OR, XOR, NOT, INC, and DEC. Simulated using SystemVerilog and ideal for learning digital design fundamentals.

Language: Verilog - Size: 569 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

SaiManojGubbala/RISC-V

A 32 Bit RISC-V Processor Implementation in Verilog

Language: Verilog - Size: 4.4 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 3 - Forks: 0

DopeBiscuit/IEEE-Digital-IC-Design

This repo is for my IEEE ASU Student Branch Digital IC Design workshop, an introduction to digital design using Verilog, this is a documentation of my tasks.

Language: Verilog - Size: 11.5 MB - Last synced at: about 2 months ago - Pushed at: about 2 years ago - Stars: 4 - Forks: 1

ananyanair31/RISC_V

5-stage pipelined RISC-V processor with instruction fetch, decode, execute, memory access, and write-back stages.

Language: Verilog - Size: 55.7 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

flasonil/Serial-Multiplier

16 bit serial multiplier in SystemVerilog

Language: SystemVerilog - Size: 165 KB - Last synced at: 5 months ago - Pushed at: about 7 years ago - Stars: 13 - Forks: 5

HopzAlot/16-bit-Pipelined-Processor-Verilog-

1st Semester Project.

Language: C - Size: 282 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Language: Verilog - Size: 173 KB - Last synced at: 7 months ago - Pushed at: almost 3 years ago - Stars: 54 - Forks: 15

luk3Sky/Building-A-Processor---Project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

Language: Verilog - Size: 880 KB - Last synced at: 8 months ago - Pushed at: almost 7 years ago - Stars: 8 - Forks: 1

TahirZia-1/UART

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: 4 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

sbaldzenka/xyloni_examples

Examples for Efinix Xyloni FPGA-board.

Language: Verilog - Size: 591 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 1

Jjateen/Snake-Game-Verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

Language: Verilog - Size: 8.63 MB - Last synced at: 8 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

MohamedHussein27/SPI_Slave_With_Single_Port_Memory

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.

Language: Verilog - Size: 2.18 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 5 - Forks: 0

ishifr/fpga_prototyping_codes

FPGA prototyping by Verilog examples kitobini o'qish davomida yozilgan kodlar to'plami. Nexys4DDR(Artix-7) dev board'dan foydalanilgan. A collection of code written while reading the book FPGA prototyping by Verilog examples. Nexys4DDR(Artix-7) dev board is used

Language: Tcl - Size: 0 Bytes - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

DarrenHuang0411/Verilog-Training-Pipeline-CPU

Verilog-Training-5-stage-Pipeline-CPU

Language: SystemVerilog - Size: 1.46 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

Abhirecket/Square-Shape-Detector

x and y are input signals representing the x and y coordinates, respectively, each being 1-bit wide.

Language: Verilog - Size: 202 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0

shreegw/FPGA-Thermostat-Controller

A Thermostat controller designed using the temperature sensor on the Nexys-4 module

Language: Verilog - Size: 104 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

MohammedS2lah/HDLBits_Verilog_Tutorials

Welcome to my repository, where I provide solutions to Verilog challenges from the HDLBits website

Language: Verilog - Size: 378 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

Touka20/DSD-THUEE

labs of Digital System Design course in 23 fall

Language: Jupyter Notebook - Size: 431 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

pescetti-studio/FliPGA01

FPGA (Verilog) implementation of the Flip01 8-bit processor.

Language: HTML - Size: 1.61 MB - Last synced at: 8 months ago - Pushed at: 10 months ago - Stars: 14 - Forks: 1

RISMicroDevices/RMR8PM3001A

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

Language: C++ - Size: 557 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 1

TKholay/HDL-Lab7-MIPSISA

The objective of this lab is to become familiar with the MIPS ISA, synthesize and implement a basic MIPS processor on the Basys3 board, learn how to use Verilog Text-IO to initialize a memory image for simulation, and extend the MIPS ISA by adding ARM-like instructions.

Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

TKholay/HDL-Lab1-CombinationalCircuits

The objective of this lab is to learn designing basic combinational circuits in Verilog and checking the correctness of the functionality using waveforms.

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TKholay/HDL-Lab2-SequentialCircuits

The objective is to design basic sequential circuits in Verilog and implementing them on an FPGA.

Language: Tcl - Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

TKholay/HDL-Lab3-Fitbit

The objective in this lab is to develop a simplified version of the activity tracking device, Fitbit, on an FPGA. The Fitbit will implement a subset of features offered by the real Fitbit device and app. A circuit that would provide input pulses to your Fitbit module will also be synthesized and implemented in this lab.

Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

TKholay/HDL-Lab4-ParkingMeter

The objective in this lab is to design (code, simulate and implement) a parking meter much like the ones around Austin. It should be able to simulate coins being added and show the appropriate time remaining. Also, it should flash slowly when less than 200 seconds are remaining and flash quickly when time has expired.

Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

TKholay/HDL-Lab5-StackCalculator

The objective of this lab is to implement a stack calculator, get more familiar with block RAMs on an FPGA and understand memory interfacing, and understand how to model buses in Verilog.

Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

TKholay/HDL-Lab6-SystolicArrayMatrixMultiplication

The objective in this lab is to perform matrix multiplication using Systolic Array structures.

Language: Verilog - Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

MohamedHussein27/RISC-V-Single-Cycle-Implementation

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book. The project includes a complete Verilog implementation, supporting various instruction types, with performance enhancements and detailed schematics for analysis.

Language: Verilog - Size: 11.4 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 0

wjjjysc/taxi

要求是起步价 3元，准行 1公里，以后 1元/公里。电机模块的跳线选择GND端，这样通过旋钮电机模块的电位器，即可达到控制电机转速的目的。另外用按键模块的KEY0来作为整个系统的复位按钮，每复位一次，计费器从头开始计费。直流电机用来模拟出租车的车轮子，每转动一圈认为是行走 1米，所以每旋转1000圈，认为车子前进1公里。系统设计是需要检测电机的转动情况，每转一周，计米计数器增加 1。七段码管显示要求为前3个显示里程，后 3个显示费用

Language: VHDL - Size: 847 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

shrujan0274/HDLBits-submissions

Solutions for 100+ questions in HDLBits using verilog

Language: Verilog - Size: 37.1 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

ultraembedded/minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

Language: Verilog - Size: 595 KB - Last synced at: 8 months ago - Pushed at: about 6 years ago - Stars: 27 - Forks: 8

mongrelgem/Verilog-Adders

Implementing Different Adder Structures in Verilog

Language: Verilog - Size: 77.1 KB - Last synced at: 9 months ago - Pushed at: about 6 years ago - Stars: 60 - Forks: 16

HIMANK729/Verilog-Projects

Implementing Verilog projects. Memory Controller,FIFO,Hamming code(error detection & correction)

Language: Verilog - Size: 108 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

ANSHVIVEKMALHOTRA/Miniproject-HEATWATCH

HEATWATCH(Temperature monitoring system)-[Digital and System Designs]

Language: Verilog - Size: 39.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 2

teekamkhandelwal/SRAM_Controller

The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.

Language: Verilog - Size: 72.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane

This is part of EC383 - Mini Project in VLSI Design.

Language: Verilog - Size: 16.6 MB - Last synced at: 6 months ago - Pushed at: over 3 years ago - Stars: 8 - Forks: 0

aekanshd/booths-multiplier-using-verilog

Language: Verilog - Size: 2.06 MB - Last synced at: 8 months ago - Pushed at: over 6 years ago - Stars: 10 - Forks: 6

afzalamu/8bit-signed-Multiplier-on-Artix7-FPGA

Verilog Code to Implementation on FPGA of 8 Bit Signed Multiplier

Language: Verilog - Size: 3.91 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

afzalamu/8Bit-signed-Full-Adder-on-ARTIX-7-FPGA

Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.

Language: Verilog - Size: 11.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

chrnthnkmutt/CarPark_Verilog

This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system

Language: Verilog - Size: 37.1 KB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

non-being/Hierarchical_design_of_Alarm_Clock_in_Verilog

Language: Verilog - Size: 13.7 KB - Last synced at: 6 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Karan-nevage/RISC-V-Single-Cycle-Core-Verilog-

This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.

Language: JavaScript - Size: 1.07 MB - Last synced at: 9 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1

yuri-panchul/tt08-adder-with-flow-control Fork of TinyTapeout/tt08-verilog-template

Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.

Language: SystemVerilog - Size: 43.9 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 1

errray/fpga-spaceship

This space ship game project, where the spaceship is positioned at the center and objects coming from different directions can be hit using FPGA buttons, has been implemented with Verilog coding in quartus environment for Altera System-on-Chip (SoC) FPGA and VGA for display.

Language: Verilog - Size: 656 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

cw1997/SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

Language: HTML - Size: 1.5 MB - Last synced at: 8 months ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 2

vSasakiv/RV32I_Processor

Risc-V 32i processor written in the Verilog HDL

Language: Verilog - Size: 6.61 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 0

sarafouad02/Multi-Clock-Domain-System-for-UART-Controlled-ALU-and-Register-Operations-in-Verilog

This system manages ALU and register file operations based on commands received via UART RX. It operates across two clock domains—one for general processing and another for UART communication. Key functions include executing arithmetic, logic, and data synchronization tasks, with results sent back through UART TX

Language: SystemVerilog - Size: 124 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

BoChen-Ye/Tiny_SoC

This is my hobby project, which contain my rsic-v core and my convolutional layer with AMBA bus

Language: Verilog - Size: 179 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

foodinsect/Advanced-Practice

This repository contains a collection of small Verilog modules for various purposes.

Language: Verilog - Size: 181 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

GirloftheLimberlost/DigitalLockFPGA

FPGA Digital Lock System with 7 Segment LED Display - Password changeable (Hexadecimal Passwords)

Size: 721 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 2

Nawras-Ahamed/ViT_AXI_IP

A ViT Hardware accelerator for improving Image inference Based on Fast Matrix multipliers and Memory management techniques , targeted for FPGAs preferably Xilinx based

Language: SystemVerilog - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

amirah-sri/all_verilog

I am trying to develop my skills through daily practice and consistency.

Language: Verilog - Size: 735 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

EhsanShahbazii/Digital-VLSI-System-Design-Projects 📦

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

Language: Verilog - Size: 73.2 KB - Last synced at: 9 months ago - Pushed at: almost 2 years ago - Stars: 7 - Forks: 0

aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

Language: Verilog - Size: 10.7 KB - Last synced at: 8 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 2

Sandy71004/Adders-Analysis-Using-Xilinx-Vivado

In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.

Size: 85 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

utkarshad21/FSM-Sequence-Detector-using-Verilog

FSM: Sequence Detector using Verilog HDL

Language: Verilog - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

utkarshad21/4-bit-Full-Adder-using-Verilog-HDL

Verilog code and testbench for 4-bit full adder

Language: Verilog - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

YajanaRao/Verilog

Verilog Programs

Language: Verilog - Size: 133 KB - Last synced at: 27 days ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

Language: Verilog - Size: 29.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 2

xkllkx/AES128_circuit

Advanced encryption standard AES128 Encryption Implementation in verilog.

Language: Verilog - Size: 94.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ErickMaRi/Proyecto-Digitales-II

Diseño de un par controlador-periférico según el protocolo MDIO (cláusula 22)

Language: Verilog - Size: 1.57 MB - Last synced at: 8 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

rishz09/digital-safe-verilog

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

Language: Tcl - Size: 2.06 MB - Last synced at: 9 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

naresh0902/Washing_Machine_Controller

A Control System for Washing Machine in Verilog HDL and DE10 Lite Board

Language: Verilog - Size: 4.42 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

aaronrjmanj/verilog

This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com

Language: Verilog - Size: 567 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0