GitHub / aaronrjmanj / verilog
This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ [email protected]
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aaronrjmanj%2Fverilog
Stars: 1
Forks: 0
Open issues: 0
License: None
Language: Verilog
Size: 567 KB
Dependencies parsed at: Pending
Created at: about 5 years ago
Updated at: 11 months ago
Pushed at: almost 4 years ago
Last synced at: 11 months ago
Topics: gvim, hdl, modelsim, questasim, verification, verilo, verilog-code, verilog-project