GitHub topics: modelsim

Repositories

Santana-DS/OAC_GRUPO-B3

OAC - Grupo B3 - Lucas Santana e Gabriel Castro (CIC0099 - UnB 2025/1)

Language: VHDL - Size: 23.6 MB - Last synced at: about 7 hours ago - Pushed at: about 8 hours ago - Stars: 0 - Forks: 0

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 2 - Forks: 0

HumbertoCG18/PUCRS-FSD-2.3-2023.24

Trabalhos, Projetos, Exercícios e aulas realizados em VHDL e Assembly na cadeira de Fundamentos de sistemas digitais, matéria do segundo semestre.

Language: VHDL - Size: 951 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 0

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.29 MB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 323 - Forks: 81

RDSik/axis-uart

AXI-Stream UART module

Language: SystemVerilog - Size: 357 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1 - Forks: 0

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.05 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 695 - Forks: 203

MUDAL/Altera_FPGA_Projects

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

Language: C - Size: 212 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 9 - Forks: 0

loykylewong/FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Language: Scala - Size: 2.95 MB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 131 - Forks: 30

SACHINUR17/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Verilog - Size: 134 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 1 - Forks: 0

Sanugiw/FPGA

UART transceiver in Verilog with TX/RX modules, testbench, FPGA implementation, 7-segment display output, and oscilloscope waveform verification.

Size: 3.49 MB - Last synced at: 22 days ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

naseridev/LogicLabWorks

A collection of digital logic circ. This project has documentation in both Persian and English

Language: HTML - Size: 271 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

MJoergen/HyperRAM

Portable HyperRAM controller

Language: VHDL - Size: 4.2 MB - Last synced at: 6 days ago - Pushed at: 7 months ago - Stars: 55 - Forks: 14

edaa-org/pyEDAA.ToolSetup

Language: Python - Size: 5.34 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 5 - Forks: 0

ItzzInfinity/100-days-of-RTL

Trying to get a new skill

Language: Verilog - Size: 79.5 MB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 23 - Forks: 6

RDSik/axis-spi

AXI-Stream SPI modules

Language: SystemVerilog - Size: 56.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

RDSik/axis-i2c-master

AXI-Stream I2C Master module

Language: SystemVerilog - Size: 275 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 2 - Forks: 0

mcquerol/electronic-systems

Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.

Size: 8.95 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

zsh811/VHDL-Digital-Clock-System

A digital clock system implemented with VHDL via Intel Quartus Prime and ModelSim.

Language: VHDL - Size: 16.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

patsaoglou/Built-In-Self-Test

Built-In-Self-Test blocks using LFSRs and MISRs for a circuit under test made in Verilog

Language: Verilog - Size: 439 KB - Last synced at: 21 days ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

patsaoglou/scan-chain

Basic scan chain block implemented in Verilog

Language: Verilog - Size: 235 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0

tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Language: SystemVerilog - Size: 820 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 275 - Forks: 60

aliaagheisX/AES

AES implementation using verilog

Language: Jupyter Notebook - Size: 535 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 2

Paebbels/JSON-for-VHDL

A JSON library implemented in VHDL.

Language: VHDL - Size: 138 KB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 78 - Forks: 17

ARC-Lab-UF/testbench-runner

Interactive testbench runner via Modelsim. Integrates with Canvas assignments.

Language: Python - Size: 7.74 MB - Last synced at: 7 days ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 1

jorgeloopzz/Multiplier

Language: VHDL - Size: 985 KB - Last synced at: 18 days ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

CFZRfrndVolt/Introducing-VHDL-

This repository contains projects and experiments focused on designing, simulating, and implementing digital circuits using VHDL (VHSIC Hardware Description Language) and Quartus II software. The projects covered in this repository serve as an introduction to key concepts in digital system design, including the creation of basic logic circuits, com

Size: 1000 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

sbaldzenka/uart_core

UART IP-core for FPGA.

Language: VHDL - Size: 26.4 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

dede6giu/ENE0040-LABSD

Compilation of codes, exercises and papers done for the electrial class ENE0040 in UnB. All was done in VHDL.

Language: VHDL - Size: 0 Bytes - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

istiak8empire/Hands-on-Project-of-Verilog-HDL

Implementing Hands-on Project of Verilog-HDL

Language: Verilog - Size: 1.98 MB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

binzakens/ET1_DT5-EFI-20231

This is an indie Electronic Fuel Injection System project that's been inherited from our sensẽi, Mr NQA. This project is a big bravo to the rest of my teammate, we've all been trying to do our best and we do.

Language: C - Size: 34.7 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

PritomP25/RISCV-Multicycle-Processor

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

Language: SystemVerilog - Size: 412 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

EngineerMichael/ModelSim-Altera-Project-Electronics-

⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.

Size: 25.4 KB - Last synced at: 4 months ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0

orcalinux/Computer-Organization-and-Architecture

Verilog code examples and materials for Computer Organization.

Language: Verilog - Size: 59.4 MB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 2

YasmeenTarek1/Smart-Parking-System Fork of maihazem607/Smart-Parking-System

An FPGA-based smart parking system that uses VHDL to simulate automated gate control, car detection, and real-time car count display with hardware integration

Language: VHDL - Size: 6.84 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2

yuravg/color_questasim

A wrapper for colorizing the output of Mentor Graphics QuestaSim messages.

Language: Perl - Size: 185 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 4 - Forks: 0

suoto/hdl_checker

Repurposing existing HDL tools to help writing better code

Language: Python - Size: 1.05 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 192 - Forks: 22

RDSik/verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

Language: Verilog - Size: 636 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0

USDA-ARS-ACSL/ExcelInterface

An excel based interface to create the input files needed for the MAIZIM model

Size: 43.9 MB - Last synced at: 3 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

RDSik/si5340-config-loader

Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface

Language: Verilog - Size: 2.15 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 1

RISCeirb/Risc-v-processor

Processor RISC-V and application

Language: C - Size: 2.43 MB - Last synced at: 4 days ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

RDSik/schoolRISCV Fork of zhelnio/schoolRISCV

CPU microarchitecture, step by step

Language: Makefile - Size: 15.3 MB - Last synced at: 9 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

VesalBargi/verilog-pipelined-cpu

A ModelSim project that implements a MIPS pipelined CPU in Verilog, enhancing efficiency through pipelining based on single-cycle CPU concepts.

Language: Verilog - Size: 135 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

VesalBargi/verilog-single-cycle-cpu

A ModelSim project that implements a MIPS single-cycle CPU using Verilog.

Language: Verilog - Size: 241 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

mehrawbmh/mini-modelsim

A very simple simulator of what Modelsim does: creating modules and gates and wires and connecting them together and see the final signal (logic) result

Language: C++ - Size: 148 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

fardinabbasi/RISC-V_Processor_Pipelined

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

Language: Verilog - Size: 883 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 6 - Forks: 1

fardinabbasi/RISC-V_Processor_SingleCycle

Design and implementation of RISC-V processor with a single-cycle datapath and controller.

Language: Verilog - Size: 1.23 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

fardinabbasi/RISC-V_Processor_MultiCycle

Design and implementation of RISC-V processor with a multi-cycle datapath and controller.

Language: Verilog - Size: 712 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0

arka-lsik/8-Bit-Natural-log-implementation

8-Bit Natural Log implementation using Verilog,

Language: Verilog - Size: 507 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

myadegari/SystemVerilog-HDL_Model_Verification

SystemVerilog modules and testbenches from the "Verification in HDL Models" course at the University of Tehran (Sep 2020 – Feb 2021), based on section 7 of "Comprehensive Functional Verification: The Complete Industry Cycle." Uses Verilog & SystemVerilog with ModelSim.

Language: Verilog - Size: 146 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

erfanasgari21/Computer_Architecture_Lab_ARM

Implementation of ARM968E-S processor for Computer Architecture Lab [Spring 2024]

Language: Verilog - Size: 4.36 MB - Last synced at: 4 months ago - Pushed at: 12 months ago - Stars: 4 - Forks: 1

esynr3z/playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

Language: Python - Size: 27.3 KB - Last synced at: 11 months ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

kajgm/ExU

RISC-V Based Execution Unit

Language: VHDL - Size: 4.49 MB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cclienti/wavedisp

Python classes to create agnostic wave files for HDL simulator viewer

Language: Python - Size: 126 KB - Last synced at: about 20 hours ago - Pushed at: over 5 years ago - Stars: 11 - Forks: 1

MJoergen/Avalon

Utilities for Avalon Memory Map

Language: VHDL - Size: 1020 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 7 - Forks: 0

sushi0706/uart

verilog-uart

Language: Verilog - Size: 359 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

JiaChangGit/IC_design-NCKU

數位IC設計 DIGITAL IC DESIGN, 陳培殷

Language: Verilog - Size: 18.5 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

jimfangx/DE2-70-Bringup

Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.

Language: C - Size: 52.4 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

aaronrjmanj/verilog

This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ [email protected]

Language: Verilog - Size: 567 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

LeoMartinezTAMUK/VHDL_LogicalEquationSim

A simple program written in VHDL used to simulate/solve the outputs of two separate logical equations both in SOP and POS simultaneously.

Language: VHDL - Size: 7.81 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

SakaSerbia/GAME-SURFER-on-VHDL-DE1-SoC

VHDL Implementation of the Game Surfer on DE1-SoC Board

Size: 14.6 KB - Last synced at: about 1 year ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0

Dipto9999/Scrolling_Display_DE1-SoC

Scrolling Display Implemented With Digital Design Concepts on De1-SoC

Language: SystemVerilog - Size: 3.09 MB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Erfangholiz/My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

Language: Verilog - Size: 383 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

DOUDIU/Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

Language: Verilog - Size: 37.8 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 17 - Forks: 0

maxdoublee/ADVANCED-VLSI-DESIGN---ECSE-6680

Max Destil's Advanced VLSI Design course project portfolio. See link for course description.

Language: MATLAB - Size: 28.2 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

RiccardoSagramoni/convolutional-code-generator 📦

University Project for "Electronics and Communication Systems" course (MSc Computer Engineering @ University of Pisa). VHDL design and logical synthesis of a convolutional code generator.

Language: VHDL - Size: 2.14 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

SiavashShams/ARM-Processor_With_Forwarding_And_SRAM

The code for the ARM processor with forwarding and SRAM, and the synthesized code for implementation on EP2C70F672C8N FPGA board programmed through Quartus II.

Language: SystemVerilog - Size: 2.44 MB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

Kazhuu/vhdl-examples

VHDL examples for a different kind of topics

Language: VHDL - Size: 79.1 KB - Last synced at: 3 months ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 1

MaorAssayag/Architecture-of-CPU-projects

VHDL , ModelSIM, Quartus, FPGA, Image Processing

Language: VHDL - Size: 128 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 14 - Forks: 3

tdurkut/BIL331

Bilgisayar Organizasyonu Verilog Projeleri

Language: Verilog - Size: 2.08 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0

Malisha4065/RISC-Processor

32 bit risc processor designed using verilog

Language: Verilog - Size: 1.04 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

dhwanish-3/Verilog-Programming-Logic-Design-Lab

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Language: Verilog - Size: 28.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Shahriar-0/Computer-Aided-Design-Course-Projects-F2024

Implementing different neural networks using hardware and ModelSim.

Language: Verilog - Size: 23 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

helakaraa/AES-Algorithm

Implementation of AES Algorithm as a custom hardware using NIOS II processor. VHDL using QUARTUS and ModelSIM.

Language: VHDL - Size: 955 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

MohammadMahdi-Abdolhosseini/Computer-Architecture-Lab

Computer Architecture Lab - Assignments - Fall 2023

Language: SystemVerilog - Size: 3.86 MB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

KatelynLam97/-Digital-Systems-Project-Microwave

Size: 84 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

sumezawa/modelsim_on_linux

ModelSim Student Edition installation tutorial for Debian-based distros

Size: 13.7 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

Shahriar-0/Computer-Architecture-Course-Projects-S2023

Verilog implementation of a DFS search and RISC-V processor in Single-Cycle, Multi-Cycle and Pipeline

Language: Verilog - Size: 13.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 1

heckerfr0d/LD_LAB

VARILAG LAGIK

Language: Verilog - Size: 2.08 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Pavithra-Rajan/LD-PD-Lab-S3

Programs in C and Verilog written as a part of Program Design Laboratory and Logic Design Laboratory offered in S4, CSE NITC.

Language: Verilog - Size: 798 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

Null3rror/Direct-Mapped-Data-Cache

Verilog Direct Access Cache Implementation

Language: Verilog - Size: 155 KB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 1

LockBall/floatfixlib_VHDL1993

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

Language: VHDL - Size: 111 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

RomeoMe5/DDLM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Language: Verilog - Size: 121 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 43 - Forks: 33

Saadia-Hassan/Real-Time-Clock-Module

A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.

Language: Verilog - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

Saadia-Hassan/Traffic-Light-Controller-Using-FSM

An automatic traffic light controller is designed and simulated using the concept of Finite State Machine in ModelSim.

Language: Verilog - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

AlexLevitin/VHDL_Encryptor_Decryptor

Encryption/Decryption unit in FPGA written in VHDL with use of test benches and simulations

Size: 14.5 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Se7ely/ModelSimMemFilesAssembler

An assembler that transfers your assembly code into .mem files for simulation in modelsim. Instruction set, opcodes assignment, and sample files included.

Language: Python - Size: 2.63 MB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

RomeoMe5/FPGA-Matrix-Base-operations

Matrix base operations on FPGA example

Language: Tcl - Size: 4.62 MB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0

Kenji-Ishimaru/msim-sample-verilog

ModelSim verilog simulation environment sample

Language: Verilog - Size: 4.88 KB - Last synced at: 5 days ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

MelvinMo/HDL_Course_Archive

This repository houses my work from the undergraduate hardware description language course in Verilog and the utilization of tools such as ModelSim and Xilinx ISE.

Language: Verilog - Size: 2.21 MB - Last synced at: 4 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0