Ecosyste.ms: Repos

An open API service providing repository metadata for many open source software ecosystems.

GitHub topics: system-verilog

Repositories

verilator/verilator

Verilator open-source SystemVerilog simulator and lint system

Language: C++ - Size: 24.7 MB - Last synced: about 8 hours ago - Pushed: about 14 hours ago - Stars: 2,200 - Forks: 536

taneroksuz/fpu

IEEE 754 floating point library in system-verilog and vhdl

Language: VHDL - Size: 210 KB - Last synced: 2 days ago - Pushed: 2 days ago - Stars: 47 - Forks: 8

taneroksuz/fpu-sp

IEEE 754 floating point library in system-verilog and vhdl

Language: VHDL - Size: 122 KB - Last synced: 2 days ago - Pushed: 2 days ago - Stars: 23 - Forks: 3

sean-galloway/RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

Language: SystemVerilog - Size: 25.1 MB - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 1 - Forks: 0

halegchen/University-Projects

Course projects, capstone and individual studies.

Language: SystemVerilog - Size: 66.4 KB - Last synced: 7 days ago - Pushed: over 4 years ago - Stars: 0 - Forks: 0

muhammadtalhasami/Axi4_lite_interface

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

Language: SystemVerilog - Size: 104 KB - Last synced: 14 days ago - Pushed: 14 days ago - Stars: 0 - Forks: 1

esynr3z/corsair

Control and Status Register map generator for HDL projects

Language: Python - Size: 687 KB - Last synced: 3 days ago - Pushed: 2 months ago - Stars: 90 - Forks: 26

seanpm2001/BootDown

An experimental operating system project that runs at the BIOs level, but can be a functional operating system.

Language: Assembly - Size: 1010 KB - Last synced: 21 days ago - Pushed: over 2 years ago - Stars: 3 - Forks: 2

shyamal-anadkat/The-11-of-us

Language: SystemVerilog - Size: 5.1 MB - Last synced: 24 days ago - Pushed: over 6 years ago - Stars: 2 - Forks: 0

iammituraj/pequeno_riscv

Pequeno aka pqr5 is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I

Language: SystemVerilog - Size: 23.4 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 11 - Forks: 1

muhammadtalhasami/RV32I_Single_Cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Language: Verilog - Size: 159 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 2 - Forks: 0

pulp-platform/trace_debugger

Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.

Language: SystemVerilog - Size: 6.87 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 13 - Forks: 6

aajibade1/MIPS-Processor

Complete design of a 32-bit 5-stage pipelined MIPS Processor with an L1 cache with snoopy coherency with achieved Gate-level Frequency of 53MHz and fully synthesised on an FPGA

Language: SystemVerilog - Size: 1.06 MB - Last synced: 3 months ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

josefdc/SystemVerilogSetup

Script de PowerShell para configurar rápidamente un entorno de desarrollo SystemVerilog, incluyendo la instalación de VS Code, extensiones relevantes y herramientas de compilación

Language: PowerShell - Size: 3.91 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 0

cvonk/FPGA_SPI

Connecting FPGA and Arduino using SPI.

Language: Verilog - Size: 2.52 MB - Last synced: 17 days ago - Pushed: about 2 years ago - Stars: 20 - Forks: 3

Nidhinchandran47/my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

Language: Verilog - Size: 1.71 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 8 - Forks: 1

poshtkohi/psml

PSML: parallel system modeling and simulation language for electronic system level

Language: C++ - Size: 8.14 MB - Last synced: 4 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 1

edaa-org/pySVModel

An abstract language model of SystemVerilog (incl. Verilog) written in Python.

Language: Python - Size: 2.79 MB - Last synced: 4 days ago - Pushed: 4 months ago - Stars: 7 - Forks: 0

dg2300/AXI_WB_TB

Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.

Language: Verilog - Size: 310 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 1 - Forks: 0

stornado/Open-IC-DEV

Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh，vscode 等开源工具链的开发环境。

Language: Dockerfile - Size: 28.3 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

minecraftdixit/Digital-ASIC-LAB

Verilog Codes for various Design for lab at IIT Jodhpur

Language: SystemVerilog - Size: 755 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

michellavezzo/clock_verilog

First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.

Language: SystemVerilog - Size: 60.5 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

RomeoMe5/DDLM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Language: Verilog - Size: 121 MB - Last synced: 7 months ago - Pushed: 8 months ago - Stars: 43 - Forks: 33

angelobacchini/mergeSort_sv

Synthesizable System Verilog implementation of bottom-up merge sort

Language: Jupyter Notebook - Size: 103 KB - Last synced: 7 months ago - Pushed: over 5 years ago - Stars: 2 - Forks: 1

nxbyte/Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Language: Verilog - Size: 2.23 MB - Last synced: 7 months ago - Pushed: over 4 years ago - Stars: 91 - Forks: 21

a-gafiyatullin/digital-design

🖥️ Digital Design and Computer Architecture

Language: SystemVerilog - Size: 888 KB - Last synced: 7 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

cvonk/FPGAmath

Verilog HDL implementations of adders/subtractor, multiplier, divider and square root. As well as HTML simulations.

Language: JavaScript - Size: 67.6 MB - Last synced: 17 days ago - Pushed: about 2 years ago - Stars: 5 - Forks: 3

patel-soham/SRAM-memory

A project to implement and test simple SRAM synchronous positive edge memory.

Language: SystemVerilog - Size: 38.1 KB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

patel-soham/interrupt-controller

A project to implement and test interrupt controller using Questasim software.

Language: Verilog - Size: 18.6 KB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

patel-soham/fifo

A project to implement and test synchronous and asynchronous FIFO using Questasim software.

Language: Verilog - Size: 44.9 KB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

auto-tb/auto-tb

auto_tb

Language: Python - Size: 78.1 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

Rohanmrao/Simple-Perceptron-using-System-Verilog

Demo of a simple 2 layer feed forward perceptron using system verilog (RISC V project)

Language: Verilog - Size: 1.8 MB - Last synced: 9 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 1

hrutik016/Verilog-SystemVerilog

This Repo contains some of my Verilog & SystemVerilog Programs.

Language: Verilog - Size: 694 KB - Last synced: 9 months ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0

zubeyir-bodur/Simple-Processor

Simple, multicycle processor in Basys3 FPGA

Language: HTML - Size: 2.25 MB - Last synced: 10 months ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0

zubeyir-bodur/Digital-Design-Labs

My Freshman & Junior year CS223, digital design, labs

Language: HTML - Size: 19.1 MB - Last synced: 10 months ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0

zubeyir-bodur/Computer-Organization-Labs

Implementations of single-cycle & pipelined processors, experiments related to cache memory and more

Language: Assembly - Size: 4.68 MB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

mamadaliev/sequent

Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog

Language: Verilog - Size: 7.81 KB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 10 - Forks: 1

mrLSD/riscv-cpu

RISC-V five stage pipline CPU

Language: SystemVerilog - Size: 6.84 KB - Last synced: 9 months ago - Pushed: almost 5 years ago - Stars: 5 - Forks: 0

gvilardefarias/Hardware-Data-Structures

A systemverilog implementation of the data structures: priority queue, queue and stack

Language: SystemVerilog - Size: 9.77 KB - Last synced: 9 months ago - Pushed: about 4 years ago - Stars: 2 - Forks: 1

zeynepCankara/Computer_Organization_Labs

My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL

Language: Assembly - Size: 5.88 MB - Last synced: about 1 year ago - Pushed: almost 5 years ago - Stars: 5 - Forks: 3

vborchsh/vloginit

Templates generator: make Verilog/SystemVerilog module template by parameters and ports list

Language: Python - Size: 15.6 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

abdullah8a0/one-chan

An FPGA-based Chess Engine and TPU

Language: SystemVerilog - Size: 137 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

jtgebert/fpganes_release

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

Language: HTML - Size: 20.5 MB - Last synced: about 1 year ago - Pushed: about 7 years ago - Stars: 33 - Forks: 14

pfnet-research/ATPG4SV

A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.

Language: OCaml - Size: 40 KB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 12 - Forks: 2

user-of-github/BSUIR_Labs_Architecture-of-computing-systems 📦

Repository for Architecture Of Computing Systems labs | Logisim & System Verilog & Assember & RISC-V

Language: Assembly - Size: 65.5 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

i3abghany/Mips32

MIPS fine-grained multithreaded, five-stage pipelined, and software-interlocked core in SystemVerilog.

Language: C - Size: 525 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

IlyaChichkov/RISC_V-CPU

Educational project which goal is realization of processor with RISC-V architecture.

Language: SystemVerilog - Size: 282 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

kinap/AES-Processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

Language: SystemVerilog - Size: 17.8 MB - Last synced: about 1 year ago - Pushed: about 7 years ago - Stars: 10 - Forks: 7

esynr3z/pyhdlsim

Example of Python and PyTest powered workflow for a HDL simulation

Language: Python - Size: 11.7 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 9 - Forks: 1

PedroHSCavalcante/basic-uvm-env

Basic UVM Environment

Language: SystemVerilog - Size: 27.3 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 1 - Forks: 1

imjp2020/UVM_FIFO_TB

This testbench is based on SV and UVM Class based to verify Verilog HDL Design

Language: SystemVerilog - Size: 22.5 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

Alireza-Zwolf/MIPS-PROCESSOR

An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.

Language: SystemVerilog - Size: 1.76 MB - Last synced: 11 months ago - Pushed: almost 2 years ago - Stars: 0 - Forks: 0

mauer4/Personal-Project-Verilog-CLOCK

This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques

Language: SystemVerilog - Size: 34.9 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

mdodovic/VLSI-Verification

Verification of Design Under the Testing

Language: SystemVerilog - Size: 223 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 1 - Forks: 0

Sh3b0/FPGA-Snake

7-segment snake using a microcontroller

Language: SystemVerilog - Size: 6.86 MB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 1 - Forks: 0

rubinsteina13/SV_DSM_CORE

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

Language: SystemVerilog - Size: 50.8 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 1

rubinsteina13/SV_I2S_RX_CORE

Synthesizable SystemVerilog IP-Core of the I2S Receiver

Language: SystemVerilog - Size: 83 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 3 - Forks: 2

JoseDavidSS/CE_Architecture1.ASIP-Image_Interpolation Fork of juanignava/ComputerArchitecture1.Project2

Segundo proyecto para el curso de Arquitectura de Computadores. La idea es hacer un ASIP (Application Specific Set Processor) que genere interpolación de imagen por medio de un compilador, código en ensamblador, un procesador pipeline y scripts en alto nivel.

Language: Python - Size: 60.1 MB - Last synced: 12 months ago - Pushed: almost 2 years ago - Stars: 1 - Forks: 0

Related Keywords

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