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GitHub / rubinsteina13 / SV_DSM_CORE

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rubinsteina13%2FSV_DSM_CORE

Stars: 2
Forks: 1
Open Issues: 0

License: mit
Language: SystemVerilog
Repo Size: 50.8 KB
Dependencies: pending

Created: almost 4 years ago
Updated: about 2 years ago
Last pushed: almost 4 years ago
Last synced: about 1 year ago

Topics: asic-design, cpld, dac, digital-signal-processing, fpga, ip-core, system-verilog, verilog

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