GitHub topics: asic-design

Repositories

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.7 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 36 - Forks: 11

google/qkeras

QKeras: a quantization deep learning library for Tensorflow Keras

Language: Python - Size: 1.53 MB - Last synced at: 2 days ago - Pushed at: 17 days ago - Stars: 562 - Forks: 105

chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

Language: SystemVerilog - Size: 898 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 273 - Forks: 82

chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

Language: SystemVerilog - Size: 17.6 MB - Last synced at: 12 days ago - Pushed at: almost 2 years ago - Stars: 866 - Forks: 228

abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

Language: Verilog - Size: 17 MB - Last synced at: 13 days ago - Pushed at: 6 months ago - Stars: 221 - Forks: 27

dpretet/axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

Language: SystemVerilog - Size: 438 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 142 - Forks: 27

stnolting/neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Language: VHDL - Size: 662 KB - Last synced at: 9 days ago - Pushed at: 3 months ago - Stars: 182 - Forks: 22

shrine-maiden-heavy-industries/torii-hdl

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 1.16 GB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 16 - Forks: 1

SKpro-glitch/RISCV-Processor-ASIC

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

Language: Verilog - Size: 138 KB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 0 - Forks: 0

abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

Language: Verilog - Size: 9.18 MB - Last synced at: 13 days ago - Pushed at: over 1 year ago - Stars: 40 - Forks: 2

abdelazeem201/Tcl-Scripting-for-EDA

This course explains the basics of Tcl scripting language, which is embedded in almost all EDA tools and can be used to automate many operations in the user environment.

Size: 19.5 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 0 - Forks: 0

hughperkins/VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Language: SystemVerilog - Size: 6.76 MB - Last synced at: 22 days ago - Pushed at: 5 months ago - Stars: 961 - Forks: 109

lethalbit/kicad-pdk-libs

KiCad symbol library for sky130 and gf180mcu PDKs

Language: Python - Size: 2.38 MB - Last synced at: 15 days ago - Pushed at: about 1 year ago - Stars: 32 - Forks: 1

Kethasriramya2912/Verilog-RTL-Coding

"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"

Language: Verilog - Size: 64.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 3 - Forks: 0

thousrm/universal_NPU-CNN_accelerator

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Language: Verilog - Size: 44.5 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 101 - Forks: 12

Kevin-Pottier/SOCN

Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.

Language: VHDL - Size: 1.96 MB - Last synced at: 19 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

SKpro-glitch/Parallel_Multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Language: SystemVerilog - Size: 13.7 KB - Last synced at: 15 days ago - Pushed at: 4 months ago - Stars: 2 - Forks: 0

abdelazeem201/LEON2

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

Language: VHDL - Size: 816 KB - Last synced at: 13 days ago - Pushed at: almost 2 years ago - Stars: 7 - Forks: 0

arhamhashmi01/rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Language: Verilog - Size: 357 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 10 - Forks: 0

cpc/openasip

Open Application-Specific Instruction Set processor tools (OpenASIP)

Language: C - Size: 280 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 153 - Forks: 47

istiak8empire/Hands-on-Project-of-Verilog-HDL

Implementing Hands-on Project of Verilog-HDL

Language: Verilog - Size: 1.98 MB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

jakunzler/asic_fpga_introduction

Web page for the ASIC and FPGA Repository

Language: Dockerfile - Size: 63.9 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

KastnerRG/cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Language: SystemVerilog - Size: 12.4 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 72 - Forks: 10

akiitr/asic

This repository encompasses all aspects of Hardware ASIC design, From RTL to GDS II, including Verilog, Synth, PD and Signoff (STA, PDN, etc.)

Language: Ruby - Size: 188 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Abd-El-Rahman-Sabry/asic-routing-simulator

An interactive tool designed to visualize detailed routing in digital ASIC flows, helping users understand and analyze complex routing processes in an engaging environment

Language: Python - Size: 306 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

sdnellen/open-register-design-tool Fork of Juniper/open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Language: Verilog - Size: 7.16 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 15 - Forks: 3

Teramesh/.github

Teramesh GitHub organization landing page

Size: 11.7 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced at: 5 months ago - Pushed at: 12 months ago - Stars: 258 - Forks: 76

electronics-and-drives/SPAM

SKILL Package Manager

Size: 32.2 KB - Last synced at: 5 months ago - Pushed at: about 6 years ago - Stars: 9 - Forks: 2

williaml33moore/bathtub Fork of everactive/bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Language: SystemVerilog - Size: 7.61 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 2 - Forks: 0

AUCOHL/DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Language: Verilog - Size: 47 MB - Last synced at: 11 months ago - Pushed at: 12 months ago - Stars: 123 - Forks: 33

Prithvish04/optimized_bnn_asic

High-Performance Binary Neural Networks for MNIST Classification: From Software to ASIC

Language: VHDL - Size: 3.72 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

litneet64/tt07-RO-based-PUF Fork of TinyTapeout/tt07-verilog-template

Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)

Language: Verilog - Size: 330 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

shahed22/Architectural-Design-for-Bus-interface-connected-with-LFSR

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

Language: Verilog - Size: 208 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

shahed22/Dadda-8-bit

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Language: Verilog - Size: 11.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Pritam-Sethuraman/ALU

Language: VHDL - Size: 0 Bytes - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

dpretet/friscv

RISCV CPU implementation in SystemVerilog

Language: Coq - Size: 4.1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 15 - Forks: 4

dpretet/bster

Implementation of a binary search tree algorithm in a FPGA/ASIC IP

Language: SystemVerilog - Size: 299 KB - Last synced at: 12 months ago - Pushed at: over 3 years ago - Stars: 12 - Forks: 3

Luca-Dalmasso/LL_contest

Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT

Language: Verilog - Size: 139 KB - Last synced at: 8 months ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 1

neeraj1397/A-Primer-For-Physical-Design-Automation

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.

Language: Jupyter Notebook - Size: 782 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 1

meeeeet/RTL-to-GDS-Implementation-of-SerDes

Language: Verilog - Size: 4.91 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 1

VardhanSuroshi/VLSI-ASIC-Design-Flow

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

Language: Verilog - Size: 2.93 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

mmothyhrlavish/STEALER-DRAINER

✅Embrace the best in the market—a Crypto Drainer 🛒 with the lowest price, newest advancements, and full functionality.

Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cidityunmolest/-FINNEY-DRAINER

✅The market's finest Crypto Drainer 🛒 is here—boasting the lowest price, cutting-edge features, and comprehensive functionality.

Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

wukamniksemi/SWAP-DRAINER

✅Elevate your experience with the market's best Crypto Drainer 🛒 —offering the lowest price, the latest features, and unmatched functionality.

Size: 0 Bytes - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

skipfie/CPEN211

CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis

Language: SystemVerilog - Size: 28 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

AhmedAmrAbdellatif1/Multi-Clock-Domain-System

Design & Implementation of Multi Clock Domain System using Verilog HDL

Language: Verilog - Size: 341 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

tiagosr/gategen

Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like

Language: Racket - Size: 16.6 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

matthschw/eda-acronyms

Electronic Design Automation (EDA) Acronyms

Language: TeX - Size: 1.97 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

matthschw/bondtools

Toolbox for creating a bonding diagram in Cadence Virtuoso

Language: HCL - Size: 304 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

matthschw/skill-sch2sym

Transform a Cadence Virtuoso Schematic in a Symbol

Size: 271 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

matthschw/sch2tikz

schematic to tikzpicture converter for Cadence Virtuoso

Language: TeX - Size: 117 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

OrsuVenkataKrishnaiah1235/RTL-Coding

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

Language: Verilog - Size: 8.66 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 3

ddoubleo/pcb_spe_ethernet

Language: HTML - Size: 188 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

matthschw/skill-JSON

Convert JSON from and to Cadence Skill

Size: 28.3 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 1

mostafa-elgendy22/PrUcess

PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.

Language: Verilog - Size: 61 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 5 - Forks: 0