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GitHub / dpretet / async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/dpretet%2Fasync_fifo
Stars: 205
Forks: 67
Open Issues: 1
License: other
Language: Verilog
Repo Size: 1.01 MB
Dependencies:
1
Created: about 7 years ago
Updated: 21 days ago
Last pushed: 23 days ago
Last synced: 21 days ago
Topics: asic, asic-design, async, cdc, cross-clock-domain, fifo, fifo-cache, fifo-queue, fpga, hdl, icarus-verilog, synthesis, verification, verilator, verilog, verilog-hdl
Funding links: https://github.com/sponsors/dpretet
Files
Dependencies
- actions/checkout v2 composite