olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1010 KB - Last synced: 14 days ago - Pushed: 15 days ago - Stars: 596 - Forks: 180

stnolting/neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Language: Verilog - Size: 176 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 39 - Forks: 9

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.13 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 277 - Forks: 76

RDSik/i2c_master

Language: Verilog - Size: 38.1 KB - Last synced: 28 days ago - Pushed: 29 days ago - Stars: 0 - Forks: 0

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 205 - Forks: 67

dpretet/svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Language: Python - Size: 175 KB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 61 - Forks: 14

nihal-ramaswamy/DDCO-project

A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.

Language: Verilog - Size: 524 KB - Last synced: about 1 month ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Language: SystemVerilog - Size: 253 KB - Last synced: 10 days ago - Pushed: over 3 years ago - Stars: 41 - Forks: 5

brown9804/Verilog_Different_Arch

Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.

Language: Verilog - Size: 4.75 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 2 - Forks: 0

msinger/dmg-sim

SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip

Language: SystemVerilog - Size: 453 KB - Last synced: 2 months ago - Pushed: 3 months ago - Stars: 5 - Forks: 1

Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

Language: Java - Size: 3.39 MB - Last synced: 3 months ago - Pushed: over 6 years ago - Stars: 15 - Forks: 1

Kyrithdagon/EE-CS120A

Language: SystemVerilog - Size: 2.21 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

jchabloz/verisocks

A generic verification interface to Icarus Verilog using TCP sockets

Language: C - Size: 371 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 3 - Forks: 0

addisonElliott/SCIC

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

Language: Verilog - Size: 3.52 MB - Last synced: 4 months ago - Pushed: over 5 years ago - Stars: 10 - Forks: 1

Ammar-Bin-Amir/Verilog_Practice

Practice Codes of Verilog Language

Language: Verilog - Size: 1.4 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 1 - Forks: 0

Essenceia/MoldUPD64

RTL implementation of a MoldUPD64 receiver.

Language: Verilog - Size: 2.68 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 2 - Forks: 1

Myaats/chip8

chip8 verilog implementation targeting the terasic de0-nano dev kit

Language: Verilog - Size: 91.8 KB - Last synced: 6 months ago - Pushed: about 4 years ago - Stars: 1 - Forks: 0

fopelite/VerilogGuides

Guides on how to install a SystemVerilog toolchain on different operating systems

Language: Shell - Size: 88.9 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 3 - Forks: 2

Fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

Language: Verilog - Size: 1.95 KB - Last synced: about 1 month ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

DvvCz/CPE-133

Language: SystemVerilog - Size: 27.3 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 1 - Forks: 0

mercury-5/Verilog-HDL

Some basic hardware and logic designs and their respective testbenches written in Verilog HDL

Language: Verilog - Size: 18.6 KB - Last synced: 7 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

TheOneKevin/icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

Language: TypeScript - Size: 586 KB - Last synced: 7 months ago - Pushed: about 1 year ago - Stars: 8 - Forks: 3

FPGAwars/toolchain-iverilog 📦

:seedling: Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS

Language: Verilog - Size: 58.6 KB - Last synced: 2 months ago - Pushed: about 2 years ago - Stars: 9 - Forks: 6

abhilash-neog/Verilog-Programming

Verilog Lab work at BITS Pilani

Language: Verilog - Size: 3.2 MB - Last synced: 9 months ago - Pushed: over 5 years ago - Stars: 0 - Forks: 0

Shreesh-Kulkarni/Hardware-Modelling-Verilog

All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL

Language: Verilog - Size: 153 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 1 - Forks: 0

ParimalaS27/Parallel-Prefix-Adder-8bit-UE19CS206-DDCOLab

This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.

Language: Verilog - Size: 497 KB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 2

sifferman/verilog_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

Language: Makefile - Size: 4.88 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

varkenvarken/robin

SoC design targeted at the IceBreaker board

Language: Assembly - Size: 7.32 MB - Last synced: 12 months ago - Pushed: about 4 years ago - Stars: 5 - Forks: 0

unixb0y/SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

Language: SystemVerilog - Size: 148 KB - Last synced: about 1 year ago - Pushed: about 6 years ago - Stars: 65 - Forks: 24

melchisedech333/verilog-experiments

:space_invader: My studies with Verilog and notions of digital systems.

Language: Verilog - Size: 391 KB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

yasnakateb/PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

Language: Verilog - Size: 55.7 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 5 - Forks: 2

yasnakateb/TrafficLightController

🚦 A digital controller to control traffic in Verilog HDL

Language: Verilog - Size: 85 KB - Last synced: about 1 year ago - Pushed: almost 5 years ago - Stars: 0 - Forks: 1

yasnakateb/WMController

✨🐾✨ A Control System for Washing Machine in Verilog HDL

Language: Verilog - Size: 242 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 2 - Forks: 1

albertxie/iverilog-tutorial

Quickstart guide on Icarus Verilog.

Language: Verilog - Size: 119 KB - Last synced: over 1 year ago - Pushed: almost 4 years ago - Stars: 32 - Forks: 9

scarv/xcrypto

XCrypto: a cryptographic ISE for RISC-V

Language: Verilog - Size: 2.03 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 81 - Forks: 10

esynr3z/playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

Language: Python - Size: 27.3 KB - Last synced: 26 days ago - Pushed: over 1 year ago - Stars: 4 - Forks: 0

VishalS-HK/DDCO-Lab-UE21CS251A

A Repo that contains the source code for Digital Design and Computer Organisation course.

Language: Verilog - Size: 11.7 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 1 - Forks: 1

yasnakateb/NoCRouter

👶🏻 My first baby steps into the world of NoC

Language: Verilog - Size: 269 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 5 - Forks: 0

aditeyabaral/DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

Language: Verilog - Size: 1.82 MB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 13 - Forks: 9

sifferman/fusesoc_template

Example of how to get started with olofk/fusesoc.

Language: Python - Size: 10.7 KB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 10 - Forks: 0

esynr3z/pyhdlsim

Example of Python and PyTest powered workflow for a HDL simulation

Language: Python - Size: 11.7 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 9 - Forks: 1

LastRagnarokkr/mips16-iverilog

A processor implementation in Icarus Verilog (iVerilog), 16bit MIPS format.

Language: Verilog - Size: 25.4 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 0 - Forks: 0

GLADICOS/SPACEWIRESYSTEMC

This is a test suit spacewire using a model on systemC with a verilog with graphical interface

Language: PHP - Size: 650 MB - Last synced: over 1 year ago - Pushed: over 1 year ago - Stars: 3 - Forks: 1

GLADICOS/UART

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

Language: Verilog - Size: 352 KB - Last synced: over 1 year ago - Pushed: over 1 year ago - Stars: 6 - Forks: 1

stnolting/icarus-verilog-prebuilt

📦 Prebuilt Icarus Verilog simulator package for x64 Linux.

Size: 31.3 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 1 - Forks: 0

yasnakateb/UARTCommunication

☎️ UART Communication Implementation in Verilog HDL

Language: Verilog - Size: 4.88 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

yasnakateb/AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

Language: Verilog - Size: 32.2 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

yasnakateb/SdramController

🛠 A SDRAM controller in Verilog HDL

Language: Verilog - Size: 47.9 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 0 - Forks: 0

SymbiFlow/XilinxUnisimLibrary Fork of Xilinx/XilinxUnisimLibrary

Apache 2.0 licensed copy of the Xilinx Unisim library.

Language: Verilog - Size: 1.9 MB - Last synced: 4 months ago - Pushed: almost 4 years ago - Stars: 8 - Forks: 1

vballoli/mips-processor

Un-pipelined partial MIPS processor implementation in Verilog

Language: Verilog - Size: 6.84 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 1 - Forks: 0

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 75.2 KB - Last synced: about 1 year ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 0

librecores/docker-tools

Just a set of Dockerfiles and tools for FuseSoC

Language: Dockerfile - Size: 19.5 KB - Last synced: about 1 month ago - Pushed: over 5 years ago - Stars: 6 - Forks: 5

paranlee/guarded_unsigned_counter

Counter with two guardians who count each bit either even or odd.

Language: Verilog - Size: 19.5 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0

RomeoMe5/HopfieldFPGA

Implementation of Hopfield network using Verilog

Language: Verilog - Size: 1.26 MB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 2 - Forks: 0

yasnakateb/FIFOMemory

📍 A FIFO Memory Implementation in Verilog HDL

Language: Verilog - Size: 128 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 1 - Forks: 0

aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

Language: Verilog - Size: 10.7 KB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 1 - Forks: 2

usman1515/Matrix-Multiplier

Language: SystemVerilog - Size: 38.1 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

ImanHosseini/SSegEmu

Emulating a seven-segment display for Verilog debugging purposes.

Language: Java - Size: 929 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 0 - Forks: 0

grant-cox/pinkyfloat

16 bit IEEE floating point implementation or the UK PinKY pipelined processsor architecture.

Size: 640 KB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 1 - Forks: 0