GitHub topics: icarus-verilog

Repositories

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.07 MB - Last synced at: 4 days ago - Pushed at: 15 days ago - Stars: 681 - Forks: 200

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.23 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 318 - Forks: 83

stnolting/neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Language: VHDL - Size: 299 KB - Last synced at: 7 days ago - Pushed at: 8 days ago - Stars: 80 - Forks: 18

dpretet/svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Language: Python - Size: 755 KB - Last synced at: 3 days ago - Pushed at: 6 months ago - Stars: 77 - Forks: 17

sifferman/fusesoc_template

Example of how to get started with olofk/fusesoc.

Language: Python - Size: 10.7 KB - Last synced at: 3 days ago - Pushed at: over 3 years ago - Stars: 17 - Forks: 0

unixb0y/SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

Language: SystemVerilog - Size: 148 KB - Last synced at: 7 days ago - Pushed at: about 7 years ago - Stars: 78 - Forks: 26

yasnakateb/UARTCommunication

☎️ UART Communication Implementation in Verilog HDL

Language: Verilog - Size: 4.88 KB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0

yasnakateb/FIFOMemory

📍 A FIFO Memory Implementation in Verilog HDL

Language: Verilog - Size: 128 KB - Last synced at: about 1 month ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0

sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

Language: SystemVerilog - Size: 253 KB - Last synced at: 3 days ago - Pushed at: over 4 years ago - Stars: 44 - Forks: 8

EDA (Exploratory Data Analysis) is a crucial step in data science where analysts investigate data sets to summarize their main characteristics. It involves using visualizations and statistical techniques to understand the data and uncover patterns, trends, and relationships within it.

Size: 1000 Bytes - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

VarshithGovi/Half-Subtractor-Design-Verilog

Gate-level implementation of a half-subtractor using Verilog, featuring a comprehensive testbench, truth table validation, and waveform analysis for beginners in digital design.

Language: Verilog - Size: 20.5 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

VarshithGovi/2bit-Ripple-Carry-Adder-Verilog

A Verilog-based implementation of a 2-bit Ripple Carry Adder with a comprehensive testbench for functional verification, ideal for beginners exploring digital design and HDL concepts. 🚀

Language: Verilog - Size: 25.4 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 75.2 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 0

VarshithGovi/Full-Adder-Design-Verilog

Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

yasnakateb/NoCRouter

👶🏻 My first baby steps into the world of NoC

Language: Verilog - Size: 269 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 11 - Forks: 2

VarshithGovi/2-to-1-Multiplexer-Design-Verilog

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

Language: Verilog - Size: 17.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

yasnakateb/PipelinedARM

💎 A 32-bit ARM Processor Implementation in Verilog HDL

Language: Verilog - Size: 55.7 KB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 19 - Forks: 3

sifferman/fusesoc_project_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

Language: Makefile - Size: 4.88 KB - Last synced at: 3 days ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

yasnakateb/WMController

✨🐾✨ A Control System for Washing Machine in Verilog HDL

Language: Verilog - Size: 242 KB - Last synced at: about 1 month ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 1

yasnakateb/TrafficLightController

🚦 A digital controller to control traffic in Verilog HDL

Language: Verilog - Size: 85 KB - Last synced at: about 1 month ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 1

yasnakateb/SdramController

🛠 A SDRAM controller in Verilog HDL

Language: Verilog - Size: 47.9 KB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

brown9804/VerilogCircuitDesignsHub

Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.

Language: Verilog - Size: 4.76 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced at: 5 months ago - Pushed at: 12 months ago - Stars: 258 - Forks: 76

arjun-mec/Digital-Combination-Lock

Verilog Implementation of a Digital Combinational Lock which unlocks when a specific 3 bit sequence is entered.

Language: Verilog - Size: 134 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

RDSik/verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

Language: Verilog - Size: 636 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0

aditeyabaral/DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

Language: Verilog - Size: 1.82 MB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 16 - Forks: 9

yasnakateb/AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

Language: Verilog - Size: 32.2 KB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0

TheOneKevin/icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

Language: TypeScript - Size: 586 KB - Last synced at: 6 months ago - Pushed at: about 2 years ago - Stars: 11 - Forks: 3

watbulb/tt-toolchain-build

A Linux-Local Installation of TT tools at version parity with TinyTapeout Selected Versions (see branch name)

Language: Shell - Size: 60.5 KB - Last synced at: 3 days ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Varunkumar0610/RISC-V-32I-5-stage-Pipeline-Core

Implementation of 5 Stage 32I RISC V Pipeline Processor.

Language: Verilog - Size: 1.44 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

esynr3z/playhdl

🪀 Tool to play with HDL (inspired by EdaPlayground)

Language: Python - Size: 27.3 KB - Last synced at: 8 months ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

Alfredosavi/tangnano-hello

Sipeed Tang Nano: Fully Opensource Toolchain for FPGA Synthesis, Place & Route, Simulation and Download/Flash.

Language: Makefile - Size: 8.79 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 1

addisonElliott/SCIC

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

Language: Verilog - Size: 3.52 MB - Last synced at: 25 days ago - Pushed at: over 6 years ago - Stars: 14 - Forks: 1

aditeyabaral/up-down-counter

A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.

Language: Verilog - Size: 10.7 KB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 2

RichaSavant/Icarus-Verilog-HDL-Logical-Circuits-2023

This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.

Language: Verilog - Size: 76.2 KB - Last synced at: about 2 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

msinger/dmg-sim

SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip

Language: SystemVerilog - Size: 453 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 5 - Forks: 1

nihal-ramaswamy/DDCO-project

A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.

Language: Verilog - Size: 524 KB - Last synced at: 12 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Kyrithdagon/EE-CS120A

Language: SystemVerilog - Size: 2.21 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

jchabloz/verisocks

A generic verification interface to Icarus Verilog using TCP sockets

Language: C - Size: 652 KB - Last synced at: 3 days ago - Pushed at: 9 days ago - Stars: 3 - Forks: 0

Ammar-Bin-Amir/Verilog_Practice

Practice Codes of Verilog Language

Language: Verilog - Size: 1.4 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Essenceia/MoldUPD64

RTL implementation of a MoldUPD64 receiver.

Language: Verilog - Size: 2.68 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

Myaats/chip8

chip8 verilog implementation targeting the terasic de0-nano dev kit

Language: Verilog - Size: 91.8 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

fopelite/VerilogGuides

Guides on how to install a SystemVerilog toolchain on different operating systems

Language: Shell - Size: 88.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 2

Fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

Language: Verilog - Size: 1.95 KB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

mercury-5/Verilog-HDL

Some basic hardware and logic designs and their respective testbenches written in Verilog HDL

Language: Verilog - Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

FPGAwars/toolchain-iverilog 📦

:seedling: Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS

Language: Verilog - Size: 58.6 KB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 9 - Forks: 6

Related Keywords

icarus-verilog 68 verilog 52 gtkwave 18 iverilog 11 fpga 11 systemverilog 11 verilog-hdl 11 verilator 9 yosys 8 vivado 7 simulation 7 asic 6 modelsim 6 hdl 6 python 5 cpu 5 digital-design 5 rtl 4 open-source 4 icarus 4 synthesis 4 docker 3 icestorm 3 xilinx 3 vlsi-design 3 testbench 3 fusesoc 3 vscode 3 waveform-analysis 3 digital-logic-design 3 uart 3 counter 3 ripple-carry-adder 2 vlsi 2 ghdl 2 mips 2 vcs 2 eda 2 logic-programming 2 uart-verilog 2 logic-circuits 2 verilog-code 2 mips-processor 2 pipeline 2 formal-verification 2 verilog-project 2 systemc 2 simulator 2 mit-license 2 lattice 2 arm 2 gate-level-simulation 2 verification 2 cocotb 2 riscv 2 vhdl 2 multiplexer 2 socket-programming 1 hft-network 1 vpi 1 itch 1 moldudp 1 moldudp64 1 ouch 1 chip8 1 de0-nano 1 de10 1 hardware-description-language 1 hardware-designs 1 apio 1 hardware-acceleration 1 labs 1 encoders 1 demultiplexer 1 decoders 1 combinational-circuit 1 arithmetic-circuits 1 adders 1 tcl 1 gate 1 digital 1 cadence 1 tangnano9k 1 tangnano 1 sipeed-tang-nano-9k 1 sipeed 1 opensource 1 altera 1 eda-playground 1 sequential 1 pes 1 flip-flop 1 circuits 1 nintendo 1 gameboy 1 game-boy 1 electronics 1 dmg-cpu 1 dmg-001 1 chip 1

GitHub topics: icarus-verilog

FPGAwars/toolchain-iverilog 📦

SymbiFlow/XilinxUnisimLibrary Fork of Xilinx/XilinxUnisimLibrary