GitHub topics: uart-verilog
ben-marshall/uart
A simple implementation of a UART modem in Verilog.
Language: Verilog - Size: 53.7 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 123 - Forks: 22
yasnakateb/UARTCommunication
☎️ UART Communication Implementation in Verilog HDL
Language: Verilog - Size: 4.88 KB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 4 - Forks: 0
TahirZia-1/UART-Transmitter-and-Receiver
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
Language: SystemVerilog - Size: 231 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
Abd-El-Rahman-Sabry/processing-unit-with-uart
This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, enabling ALU operations, register file access, and data transmission. It's designed for embedded systems and educational purposes.
Language: Verilog - Size: 1.79 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
Wissance/QuickRS232
A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX
Language: Verilog - Size: 739 KB - Last synced at: about 1 month ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0
addisonElliott/LogiFindFPGATest
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
Language: Verilog - Size: 1.7 MB - Last synced at: about 1 month ago - Pushed at: over 5 years ago - Stars: 7 - Forks: 3
pConst/basic_verilog
Must-have verilog systemverilog modules
Language: Verilog - Size: 54.2 MB - Last synced at: 7 months ago - Pushed at: 10 months ago - Stars: 1,627 - Forks: 376
ZipCPU/wbuart32
A simple, basic, formally verified UART controller
Language: Verilog - Size: 1.19 MB - Last synced at: 9 months ago - Pushed at: over 1 year ago - Stars: 266 - Forks: 46
sushi0706/uart
verilog-uart
Language: Verilog - Size: 359 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
mwbryant/uart-CI
Basic continous integration testing for verilog projects
Language: C++ - Size: 6.84 KB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
Shubhayu-Das/VL504-project
Displaying images taken from an OV7670/laptop camera
Language: Python - Size: 26.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
0marAmr/UART-Interface
Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL
Language: Verilog - Size: 1.31 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
TheLeopardsH/UART
Universal Asynchronous Receiver Transmitter
Language: Verilog - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0
STjurny/BasicUART
Small light-weight implementation of UART in Verilog.
Language: Verilog - Size: 60.5 KB - Last synced at: 7 days ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1
kishanpatelec/UART-for-bluetooth-module
Language: Verilog - Size: 16.6 KB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 0
djkabutar/test_mipi_encoder_decoder
MIPI to multiple peripheral (UART, I2C, SPI, 1-Wire)
Language: Verilog - Size: 23.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
meeeeet/UART-DesignAndVerification
Language: SystemVerilog - Size: 79.1 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
RISCY-Lib/LayersOnLayers
A example of UVM Sequence Layering using UART
Size: 23.4 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
TimRudy/uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
Language: Verilog - Size: 26.7 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
kamalrajnegi/uart-verilog
Verilog description of UART and it's implementation of Artix-7 based FPGA board
Size: 1000 Bytes - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
BrunoBMoura/BM_CORE
Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.
Language: Verilog - Size: 6.14 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 1
GLADICOS/UART
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
Language: Verilog - Size: 352 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 1
mengstr/vuart
WIP - Smallish UART written in Verilog
Language: Verilog - Size: 445 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
