GitHub / pConst / basic_verilog
Must-have verilog systemverilog modules
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Stars: 1,627
Forks: 376
Open issues: 0
License: None
Language: Verilog
Size: 54.2 MB
Dependencies parsed at: Pending
Created at: over 9 years ago
Updated at: 7 months ago
Pushed at: 10 months ago
Last synced at: 7 months ago
Topics: altera, debounce, delay, encoder, fifo, fpga, hls, pwm, spi-interface, spi-master, synchronizer, tcl, uart, uart-controller, uart-protocol, uart-receiver, uart-tx, uart-verilog, verilog, xilinx
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