GitHub topics: fpga
MatthieuMichon/xlnx_fpln
Generate and build Vivado projects for all supported parts
Language: Tcl - Size: 8.79 KB - Last synced at: 38 minutes ago - Pushed at: about 2 hours ago - Stars: 1 - Forks: 0
naim75035/gfd
🔍 Explore and manage data with gfd, a streamlined tool for efficient data analysis and visualization, enhancing insights and decision-making.
Size: 1.29 MB - Last synced at: about 2 hours ago - Pushed at: about 4 hours ago - Stars: 0 - Forks: 0
nickg/nvc
VHDL compiler and simulator
Language: C - Size: 26.9 MB - Last synced at: about 5 hours ago - Pushed at: about 7 hours ago - Stars: 749 - Forks: 95
superblar/IOMMU-VTD-Bypass
🛡️ Bypass IOMMU VTD for enhanced security in virtualization, allowing controlled access to hardware while minimizing visibility in Windows environments.
Size: 5.86 KB - Last synced at: about 5 hours ago - Pushed at: about 7 hours ago - Stars: 0 - Forks: 0
arc-research-lab/CHARM
CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
Language: C++ - Size: 244 MB - Last synced at: about 8 hours ago - Pushed at: about 10 hours ago - Stars: 158 - Forks: 22
chili-chips-ba/wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
Language: Verilog - Size: 1.98 GB - Last synced at: about 11 hours ago - Pushed at: about 12 hours ago - Stars: 1,234 - Forks: 27
iammituraj/fifo
Synchronous FIFOs designed in Verilog/System Verilog.
Language: SystemVerilog - Size: 78.1 KB - Last synced at: about 13 hours ago - Pushed at: about 14 hours ago - Stars: 19 - Forks: 8
michael-lehn/ulm-on-ice
ULM (Ulm Lecture Machine) on ice40
Language: SystemVerilog - Size: 45.6 MB - Last synced at: about 14 hours ago - Pushed at: about 16 hours ago - Stars: 6 - Forks: 0
chrisgleissner/c64stream
C64 Stream is an OBS Studio source plugin for streaming video and audio from Commodore 64 Ultimate devices
Language: C - Size: 60.9 MB - Last synced at: about 16 hours ago - Pushed at: about 16 hours ago - Stars: 4 - Forks: 0
Dollar227/Squishy
🛠️ Simplify Minecraft plugin development with Squishy, a unified Kotlin API for PaperMC and SpongeMC, minimizing boilerplate and maximizing control.
Language: Kotlin - Size: 604 KB - Last synced at: about 16 hours ago - Pushed at: about 17 hours ago - Stars: 0 - Forks: 0
Miguel-1616/PPU-LITE
🔧 Build a cost-effective, clock-accurate FPGA replacement for PPU, designed to fit original consoles using a simplified, double-sided PCB.
Language: Verilog - Size: 2.22 MB - Last synced at: about 21 hours ago - Pushed at: about 23 hours ago - Stars: 0 - Forks: 0
MiSTle-Dev/FPGA-Companion
Microcontroller firmware for retro FPGA support MCUs
Language: C - Size: 4.19 MB - Last synced at: about 21 hours ago - Pushed at: about 23 hours ago - Stars: 65 - Forks: 14
f32c/tools
ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)
Language: C - Size: 521 KB - Last synced at: about 22 hours ago - Pushed at: 1 day ago - Stars: 22 - Forks: 16
analogdevicesinc/hdl
HDL libraries and projects
Language: Verilog - Size: 106 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,768 - Forks: 1,604
clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Language: Haskell - Size: 20.1 MB - Last synced at: about 19 hours ago - Pushed at: about 21 hours ago - Stars: 1,551 - Forks: 164
avaycele/TangNano9K-Frenzy
🎮 Port Frenzy Arcade VHDL code to Tang Nano 9K FPGA for seamless VGA monitor compatibility, enhancing your gaming experience effortlessly.
Language: Shell - Size: 1.82 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0
aibarr23/Embedded-Control-Robotics-PLC
Everything Embedded to FPGA including RTOS and ROS2; and industrial automation
Language: C - Size: 26.2 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0
msinger/gbreveng
Stuff for Gameboy reverse engineering and some documentation
Language: SystemVerilog - Size: 143 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 5 - Forks: 0
miguelmagv/verilog-flm
⚙️ Simplify Verilog design and simulation with verilog-flm, a lightweight framework that enhances your workflow and boosts productivity.
Size: 1.29 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0
fastmachinelearning/hls4ml
Machine learning on FPGAs using HLS
Language: Python - Size: 260 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,675 - Forks: 482
true-grue/Brus-16
A tiny game console for education
Language: Python - Size: 130 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 12 - Forks: 0
verilog-to-routing/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language: C++ - Size: 350 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,156 - Forks: 430
FPGAwars/apio
:seedling: Open source ecosystem for open FPGA boards
Language: Python - Size: 149 MB - Last synced at: about 23 hours ago - Pushed at: 1 day ago - Stars: 905 - Forks: 152
jotego/jtcores
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
Language: Verilog - Size: 314 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 277 - Forks: 46
fpgasystems/Coyote
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
Language: SystemVerilog - Size: 663 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 305 - Forks: 88
ikwzm/FPGA-SoC-Debian13
Debian12 Boot Image (U-boot, Linux Kernel, Debian13 RootFS) for ZYBO/ZYBO-Z7/PYNQ-Z1/DE10-Nano/DE0-Nano-SoC
Size: 408 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
ravez24/verilog-c2w
🎛️ Convert Verilog code to C for efficient simulation and synthesis, streamlining design workflows and enhancing hardware development processes.
Size: 1.29 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 1
Opvenom1001/vhdl-yr7
🚀 Explore VHDL designs for Year 7 projects, enhancing learning in digital logic through hands-on examples and simulations.
Size: 1.29 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
Kilo9000/TangNano9K-Apple1
🖥️ Port Apple 1 computer code to Tang Nano 9K FPGA for seamless VGA monitor experience, leveraging original work by Alan & Niels for easy access and enjoyment.
Language: Verilog - Size: 1.76 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
fpga-spelling/fpga-spelling
Dictionary for spell checking of FPGA code.
Size: 299 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 5 - Forks: 0
fastmachinelearning/qonnx
QONNX: Arbitrary-Precision Quantized Neural Networks in ONNX
Language: Python - Size: 5.57 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 163 - Forks: 53
spcl/dace
DaCe - Data Centric Parallel Programming
Language: Python - Size: 153 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 557 - Forks: 145
mit41301/BASIC-52_CYCLONE-IV_EP4CE6E22C8
BASIC-52 running on Cyclone IV at 11.0592, 25 and 50 MHz. EPCS4 configuration flash. 50MHz oscillator pin 24 used. 27 MHz unused.
Language: BASIC - Size: 490 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
walletmfi/c64stream
🎮 Stream video and audio from your Commodore 64 Ultimate to OBS Studio over your network, eliminating capture cards for seamless recording and broadcasting.
Language: C - Size: 7.18 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0
shivammmmg/fpga-arithmetic-calculator-verilog
A 4-bit arithmetic calculator built in Verilog on the Intel DE10-Lite FPGA. Performs addition and two’s-complement subtraction with results displayed on seven-segment LEDs.
Language: Verilog - Size: 6.84 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
openwall/john
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
Language: C - Size: 127 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 12,153 - Forks: 2,366
Stephanie758/Half_Adder_Verilog_Code_Xilinx_Vivado
🔧 Explore Verilog code for a Half Adder with testbench and simulation results, designed for Xilinx Vivado. Perfect for learning digital design fundamentals.
Language: JavaScript - Size: 1.62 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
Kuykakuy/ecp5-hello
👋 Simplify ECP5 FPGA development with this project, offering an easy-to-use template for quick setups and efficient design workflows.
Language: Makefile - Size: 1.34 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
hsgofficial/TangNano9K-Gottlieb_MA55
🐙 Tang Nano 9K port of Gottlieb MA55 sound board. VHDL code ported to FPGA with work by James Sweet; open hardware for arcade audio.
Language: VHDL - Size: 487 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 2 - Forks: 0
thomas636b/Johnson-HRNG
Johnson-Nyquist Noise Based Multi-Purpose Hardware Random Number Generator
Size: 1.95 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0
Xilinx/XRT
Run Time for AIE and FPGA based platforms
Language: C++ - Size: 127 MB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 629 - Forks: 505
ateo44/vhdl-5sv
🔧 Enhance your VHDL designs with vhdl-5sv, a streamlined tool for efficient simulation and verification of VHDL code.
Size: 1.29 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
flychair/Patent_US20240086445-GenAI-Diagnostic_Agent
🤖 Automate failure detection and resolution in integrated circuits and SoC platforms with an AI-driven diagnostic agent for efficient troubleshooting.
Size: 6.84 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
ryad23r/vhdl-p5v
🚀 Design and simulate digital circuits with VHDL using p5.js for interactive visualizations and educational insights.
Size: 1.29 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
hardikk1945/system-design-fundamentals
📚 Master system design concepts and patterns to ace interviews and build scalable systems through structured guides and real-world case studies.
Size: 1.3 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
joseph-kivuva/TangNano9K-Arcade
🎮 Build your own arcade experience with the Tang Nano 9K Arcade PCB, featuring 8-bit VGA, PS2 keyboard support, and dual-channel audio.
Size: 2.17 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0
robinlebon/TangNano9K-Centipede
🎮 Port Centipede arcade VHDL code to the Tang Nano 9K FPGA Board for seamless VGA monitor integration by Pinballwiz.org.
Language: Verilog - Size: 1.83 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
abdelazeem201/ASIC-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Language: Verilog - Size: 5.77 MB - Last synced at: 2 days ago - Pushed at: 4 months ago - Stars: 412 - Forks: 56
MPSU/APS
Методические материалы по разработке процессора архитектуры RISC-V
Language: SystemVerilog - Size: 117 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 281 - Forks: 69
iRituzenRayobej/Luna
🌙 Generate concise commit messages for Git with Luna, utilizing the Google Gemini 2.0 Flash API for efficient version control.
Language: Go - Size: 5.84 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0
Kushagra1A/openpi
🤖 Explore open-source robotics models and packages, including advanced vision-language-action systems for versatile applications and fine-tuning options.
Language: Python - Size: 792 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0
iamlopez2512/vhdl-dsp-building-blocks
🔧 Build VHDL digital design blocks with modular exercises covering combinational logic, sequential circuits, filters, and IP core integration.
Language: VHDL - Size: 1.95 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 1
amba230/TangNano9K-Galaga
Language: VHDL - Size: 1.84 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0
Wayrix70/pytcl
Read-only mirror of https://gitlab.com/tymonx/pytcl
Language: Python - Size: 26.4 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 1
Gonsukey/verilog-uhj
🛠️ Streamline your hardware design with Verilog-UHJ, an efficient framework for creating and managing digital circuit simulations.
Size: 1.29 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
alikhaled14589653/DE2-MissileCommand
Missile Command Arcade synthesized on an Altera DE2-35 Dev Board.
Language: Verilog - Size: 246 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
saadelahii/JTAG-IEEE-1149.1
Basic JTAG standard implementation in Verilog and integration with a CUT
Language: Verilog - Size: 1.01 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 2 - Forks: 1
tanzimyasr/luna
Self-Hosted Calendar Aggregator and Frontend
Language: Go - Size: 325 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 1
mushr00ma/cloud-simulations
This repository features 15 Python programs simulating cloud computing concepts like task scheduling, load balancing, virtualization, and more. It’s a handy resource to grasp distributed computing, fault tolerance, and scalability in modern cloud infrastructure.
Language: Python - Size: 28.3 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
Bhonesh/power-optimized-riscv
⚙️ Optimize power consumption with a 3-stage pipelined RISC-V processor, designed for energy efficiency through advanced clock and data gating techniques.
Language: Verilog - Size: 1.48 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 1
soltana11/TangNano9K-Invaders2
Tang Nano 9K Space Invaders Part II ports a VHDL arcade game to the Tang Nano 9K FPGA, playable on VGA displays 🐙.
Language: VHDL - Size: 562 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 2 - Forks: 0
soni3006/basic_logic_gates_with_verilog
basic logic gates are implemented using verilog languege and simulation is done in xilinx vivado
Language: JavaScript - Size: 75.2 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0
UCSBarchlab/pyrtlnet
A hardware implementation of quantized neural network inference in the PyRTL hardware description language.
Language: Python - Size: 1.05 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 8 - Forks: 1
carlosedp/chiselv
A RISC-V Core (RV32I) written in Chisel HDL
Language: Scala - Size: 542 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 105 - Forks: 20
nikolozi93/verilog-3ai
🔧 Simplify Verilog design with AI-driven tools for automated code generation, validation, and optimization in digital circuit projects.
Size: 1.29 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 1
Fraunhofer-IMS/riscv_lab
under construction... :construction:
Language: Tcl - Size: 391 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0
one-ware/OneWare
Next Generation IDE for Electronics Development
Language: C# - Size: 7.33 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 110 - Forks: 12
kactus2/kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Language: C++ - Size: 147 MB - Last synced at: 1 day ago - Pushed at: 3 days ago - Stars: 236 - Forks: 43
zangman/de10-nano
Absolute beginner's guide to the de10-nano
Language: Shell - Size: 10.2 MB - Last synced at: 3 days ago - Pushed at: 8 months ago - Stars: 247 - Forks: 55
openhwgroup/cva6
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
Language: Assembly - Size: 140 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 2,651 - Forks: 842
chili-chips-ba/openCologne-PCIE
The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog with best-in-class VIP, Slot and M.2 cards for GateMate, the project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI, ...
Language: C++ - Size: 64.2 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 37 - Forks: 1
kelu124/echomods
Open source ultrasound processing modules and building blocks
Language: Jupyter Notebook - Size: 2.87 GB - Last synced at: 4 days ago - Pushed at: 5 months ago - Stars: 387 - Forks: 111
chili-chips-ba/openPCIE
Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensource on the Host side too! Our project roots for Root Port in 4 ways: 1) openRTL; 2) openBFM with unique SIM setup, way faster than vendor's; 3) openSW stack; 4) one-of-a-kind openBackplane.
Language: HTML - Size: 172 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 36 - Forks: 3
adilsondias-engineer/fpga-learning
Learning FPGA development for low-latency trading systems. Projects progress from fundamentals to trading-relevant concepts like high-speed data processing, protocol implementation, and hardware acceleration.
Language: Tcl - Size: 43.3 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0
splinedrive/kianRiscV
RISC-V XV6/Linux SoC, marchID: 0x2b
Language: Verilog - Size: 200 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 982 - Forks: 68
Xilinx/RapidWright
Build Customized FPGA Implementations for Vivado
Language: Java - Size: 8.17 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 341 - Forks: 121
amigavision/amigavision.github.io
Web site for amiga.vision
Language: HTML - Size: 19.9 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0
nachoborgatello/tp1_alu
Trabajo Práctico N.º 1 - Arquitectura de Computadoras
Language: Tcl - Size: 2.4 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0
slaclab/surf
A huge VHDL library for FPGA and digital ASIC development
Language: VHDL - Size: 182 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 403 - Forks: 77
JesusGMR96/SystemVerilog-Neural-Networks
SystemVerilog implementations of fundamental neural network structures, designed for synthesis on FPGAs.
Language: SystemVerilog - Size: 120 KB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0
GlasgowEmbedded/glasgow
Scots Army Knife for electronics
Language: Python - Size: 47.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2,064 - Forks: 225
danilosramos/digital-logic-vhdl
Projetos de Lógica Digital e Design de Hardware utilizando a linguagem VHDL.
Language: HTML - Size: 574 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0
ben-marshall/uart
A simple implementation of a UART modem in Verilog.
Language: Verilog - Size: 53.7 KB - Last synced at: 4 days ago - Pushed at: almost 4 years ago - Stars: 160 - Forks: 25
open-neuromorphic/awesome-neuromorphic-hw
Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.
Size: 179 KB - Last synced at: 1 day ago - Pushed at: almost 2 years ago - Stars: 190 - Forks: 21
emsec/hal
HAL – The Hardware Analyzer
Language: C++ - Size: 3.33 GB - Last synced at: 2 days ago - Pushed at: 4 days ago - Stars: 692 - Forks: 88
SpinalHDL/SpinalHDL
Scala based HDL
Language: Scala - Size: 85 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,864 - Forks: 362
emmercm/igir
🕹 A zero-setup ROM collection manager that sorts, filters, extracts or archives, patches, and reports on collections of any size on any OS.
Language: TypeScript - Size: 49.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 642 - Forks: 31
thesps/conifer
Fast inference of Boosted Decision Trees in FPGAs
Language: Python - Size: 59.8 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 57 - Forks: 31
habbi003/TangNano9K-SuperGlob
🎮 Port Super Glob arcade VHDL code to Tang Nano 9K FPGA for VGA display, enhancing retro gaming experiences with Pinballwiz.org's reliable implementation.
Language: VHDL - Size: 1.87 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0
PaddlePaddle/Paddle-Lite
PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）
Language: C++ - Size: 314 MB - Last synced at: 5 days ago - Pushed at: 5 months ago - Stars: 7,167 - Forks: 1,627
kuznia-rdzeni/transactron
Hardware transactions library for Amaranth
Language: Python - Size: 48.9 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 20 - Forks: 6
seieric/eeic-exp-fpga-adaptive-thresholding
2025A eeic-exp
Language: Verilog - Size: 227 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0
jzhs/sap-1-1
Malvino SAP-1 computer on Basys3 fpga
Language: Verilog - Size: 11.7 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0
xoozjay/digital-clock-fpga
FPGA Digital Clock using Digilent Nexy4 DDR (Project for Digital Electronics) 数字电子技术基础大作业 数字钟
Language: Verilog - Size: 27.3 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 0
libmir/dcompute
DCompute: Native execution of D on GPUs and other Accelerators
Language: D - Size: 169 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 137 - Forks: 28
jeffreyc-dev/rv32i_single_cycle_cpu
A single-cycle implementation of the 32-bit RISC-V RV32I instruction set (Integer Extension) in SystemVerilog for learning datapath and control signal flow.
Language: Assembly - Size: 610 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0
Nic30/hdlConvertorAst
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Language: Python - Size: 796 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 41 - Forks: 11
hstarmans/hexastorm
Amaranth HDL framework for laser scanner with motion control
Language: Python - Size: 4.57 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 30 - Forks: 4
olofk/serv
SERV - The SErial RISC-V CPU
Language: Verilog - Size: 12.5 MB - Last synced at: 4 days ago - Pushed at: 15 days ago - Stars: 1,661 - Forks: 231
ritartistry/HAL
HAL is a secure HTTP API Layer for Large Language Models, enabling seamless web API interactions and automatic tool generation from OpenAPI specs. 🚀🌐
Language: JavaScript - Size: 1.47 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0
