GitHub topics: fpga

Repositories

AliQorbaniFard/basic_logic_gates_with_verilog

basic logic gates are implemented using verilog languege and simulation is done in xilinx vivado

Language: JavaScript - Size: 0 Bytes - Last synced at: about 12 hours ago - Pushed at: about 13 hours ago - Stars: 1 - Forks: 0

machdyne/zeitlos

Zeitlos SOC/OS

Language: Verilog - Size: 991 KB - Last synced at: about 17 hours ago - Pushed at: about 18 hours ago - Stars: 2 - Forks: 0

trabucayre/openFPGALoader

Universal utility for programming FPGA

Language: C++ - Size: 7.05 MB - Last synced at: about 19 hours ago - Pushed at: about 20 hours ago - Stars: 1,319 - Forks: 289

JuanCantu1/Interactive-Memory-Game

Interactive memory game implemented in Verilog and deployed on Nexys-A7 FPGA using FSM-based logic.

Language: Verilog - Size: 22.6 MB - Last synced at: about 21 hours ago - Pushed at: about 22 hours ago - Stars: 2 - Forks: 0

jotego/jtbin

Binary files for MiSTerFPGA, Pocket and other platforms

Language: Arc - Size: 6.01 GB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 266 - Forks: 71

hstarmans/hexastorm

Amaranth HDL framework for laser scanner with motion control

Language: Python - Size: 4.42 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 28 - Forks: 4

XedaHQ/xeda

Cross EDA Abstraction and Automation

Language: Python - Size: 125 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 38 - Forks: 5

jotego/jtcores

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

Language: Verilog - Size: 305 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 263 - Forks: 45

crossroadsfpga/enso

Ensō is a high-performance streaming interface for NIC-application communication.

Language: SystemVerilog - Size: 3.86 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 72 - Forks: 7

SpinalHDL/SpinalHDL

Scala based HDL

Language: Scala - Size: 81.2 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,781 - Forks: 346

JN513/Grande-Risco-5

Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.

Language: SystemVerilog - Size: 608 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 7 - Forks: 0

olofk/serv

SERV - The SErial RISC-V CPU

Language: Verilog - Size: 12.3 MB - Last synced at: about 11 hours ago - Pushed at: 2 days ago - Stars: 1,576 - Forks: 218

FPGAwars/apio

:seedling: Open source ecosystem for open FPGA boards

Language: Verilog - Size: 146 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 843 - Forks: 144

iHalt10/vnp4_framework

Vites Netwarking P4 Framework

Language: SystemVerilog - Size: 333 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 2 - Forks: 0

YoWASP/yosys

Unofficial Yosys WebAssembly packages

Language: Python - Size: 269 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 70 - Forks: 2

MUDAL/Altera_FPGA_Projects

This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.

Language: C - Size: 212 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 7 - Forks: 0

regymm/GenZ

The open-source Zynq 7000 BSP generator for openXC7

Language: C - Size: 2.54 MB - Last synced at: 2 days ago - Pushed at: 4 months ago - Stars: 33 - Forks: 1

cornell-zhang/allo

Allo: A Programming Model for Composable Accelerator Design

Language: Python - Size: 4.38 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 228 - Forks: 39

open-neuromorphic/awesome-neuromorphic-hw

Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.

Size: 179 KB - Last synced at: about 10 hours ago - Pushed at: over 1 year ago - Stars: 162 - Forks: 16

uio33/Kintex-7-MIPI-DSI-5.5-inch-4K-LCD

Kintex 7 MIPI DSI 5.5" 4K LCD

Size: 2.64 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

Language: VHDL - Size: 14 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 770 - Forks: 273

alghasi/PYNQ-FFT

ZYNQ 7020 ZTURN PYNQ, FFT & DMA in PYNQ

Language: Jupyter Notebook - Size: 545 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

Lucasdk500/FPGA-LCD-MIPI-or-DPI

FPGA MIPI DSI

Size: 6.95 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Language: VHDL - Size: 76.2 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 653 - Forks: 50

siliconcompiler/siliconcompiler

Modular hardware build system

Language: Python - Size: 335 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 987 - Forks: 99

Parretto/DisplayPort

DisplayPort IP-core

Language: SystemVerilog - Size: 6.99 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 63 - Forks: 11

PaddlePaddle/Paddle-Lite

PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

Language: C++ - Size: 314 MB - Last synced at: about 2 hours ago - Pushed at: 17 days ago - Stars: 7,079 - Forks: 1,619

kactus2/kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Language: C++ - Size: 146 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 206 - Forks: 39

logisim-evolution/logisim-evolution

Digital logic design tool and simulator

Language: Java - Size: 108 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 5,724 - Forks: 724

f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Language: Jupyter Notebook - Size: 9.52 MB - Last synced at: 2 days ago - Pushed at: 3 days ago - Stars: 283 - Forks: 113

analogdevicesinc/hdl

HDL libraries and projects

Language: Verilog - Size: 83 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,636 - Forks: 1,565

This repository features 15 Python programs simulating cloud computing concepts like task scheduling, load balancing, virtualization, and more. It’s a handy resource to grasp distributed computing, fault tolerance, and scalability in modern cloud infrastructure.

Language: Python - Size: 28.3 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

Laavaan-J/Kintex-7-MIPI-DSI-5.5-inch-2K-LCD

Kintex 7 MIPI DSI 5.5" 2K LCD

Size: 1.17 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

BerkeleyLab/Marble

Dual FMC FPGA carrier board developed for general purpose use in particle accelerator electronics instrumentation.

Language: Python - Size: 193 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 25 - Forks: 8

t-weber/electro

Electronics projects.

Language: C++ - Size: 760 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

nachoborgatello/tp3_mips

Trabajo Práctico N.º 3 - Arquitectura de Computadoras

Language: Shell - Size: 1.01 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Language: C++ - Size: 313 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1,086 - Forks: 411

amigavision/amigavision.github.io

Web site for amiga.vision

Language: HTML - Size: 16.1 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

Unicamp-Odhin/SPI-Slave

SPI Slave module written in SystemVerilog HDL

Language: Tcl - Size: 38.1 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

lauterbach-mirror/polarfire_trace

Language: VHDL - Size: 85.9 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

perehinik/Logic_Analyzer_PCB

KiCad PCB project of Logic Analyzer

Language: ANTLR - Size: 49.8 MB - Last synced at: about 16 hours ago - Pushed at: over 4 years ago - Stars: 40 - Forks: 7

openwall/john

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Language: C - Size: 126 MB - Last synced at: 4 days ago - Pushed at: 10 days ago - Stars: 11,287 - Forks: 2,224

quentinprieels/rfnoc-ofdm

An RFNoC OOT module for implementing an OFDM receiver on USRP devices, as part of my master thesis.

Language: Python - Size: 347 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

philiprbrenan/btreeBlock

An implementation of the B-Tree algorithm in synthesized, placed and routed Verilog.

Language: Java - Size: 101 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 1

VCTLabs/embedded-overlay Fork of steev/python-overlay

Portage overlay for embedded/python tools and libraries

Language: Shell - Size: 1010 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 2 - Forks: 1

MiSTeX-devel/MiSTeX-hardware

Hardware for MiSTeX

Size: 70.5 MB - Last synced at: 3 days ago - Pushed at: 12 months ago - Stars: 71 - Forks: 5

TotoroTron/place-and-route

MS Technical Paper - A study on placement algorithms for heterogeneous FPGAs.

Language: Verilog - Size: 2.39 GB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 1

oneapi-src/oneAPI-samples

Samples for Intel® oneAPI Toolkits

Language: C++ - Size: 410 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1,027 - Forks: 724

emsec/hal

HAL – The Hardware Analyzer

Language: C++ - Size: 3.08 GB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 664 - Forks: 85

abdelazeem201/ASIC-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

Language: Verilog - Size: 5.75 MB - Last synced at: 1 day ago - Pushed at: 8 months ago - Stars: 327 - Forks: 42

johnnycubides/digital-electronic-1-101

Language: Verilog - Size: 39.5 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 6 - Forks: 2

Xilinx/finn

Dataflow compiler for QNN inference on FPGAs

Language: Python - Size: 84.6 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 819 - Forks: 256

vossstef/VIC20Nano

Commodore VIC20 core for the Tang Nano 9k Nano 20k Primer 20k Primer 25k Mega 60k Mega138k Pro Console60k FPGA

Language: VHDL - Size: 38.1 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 14 - Forks: 2

OpenEDF/verilog-basic

learn the combinational and sequential logic circuit.

Language: SystemVerilog - Size: 24.3 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 15 - Forks: 1

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

Xilinx/brevitas

Brevitas: neural network quantization in PyTorch

Language: Python - Size: 20.2 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1,304 - Forks: 212

f32c/f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

Language: C - Size: 11.6 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 413 - Forks: 105

open-sdr/openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Language: C - Size: 24.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 4,143 - Forks: 701

HEP-SoC/SoCMake

CMake based hardware build system

Language: CMake - Size: 6.05 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 17 - Forks: 3

FPGALUAN/Level_0_KV260_FPGA

A sample FPGA project on KV260

Language: C - Size: 74.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 21 - Forks: 3

briansune/Kintex-7-MIPI-DSI-5.5-inch-4K-LCD

Kintex 7 MIPI DSI 5.5" 4K LCD

Size: 2.64 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0

pulp-platform/carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Language: Tcl - Size: 2.21 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 96 - Forks: 18

briansune/FPGA-TFT-MIPI-or-DPI

FPGA TFT MIPI DSI Verilog Examples

Size: 8.77 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0

epsilon537/boxlambda

FPGA based microcomputer sandbox for software and RTL experimentation

Language: VHDL - Size: 570 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 55 - Forks: 0

regymm/PYNQSDR

PYNQ-Z1 + AD936X openwifi capable SDR platform

Size: 9.23 MB - Last synced at: 2 days ago - Pushed at: over 2 years ago - Stars: 89 - Forks: 16

XdpCs/HDU-computer-organization

杭州电子科技大学计算机组成实验：代码和解析

Language: C - Size: 5.76 MB - Last synced at: 2 days ago - Pushed at: about 1 year ago - Stars: 51 - Forks: 7

harbaum/MiSTeryNano

Atari STE MiSTery core for the Tang Nano FPGAs

Language: SystemVerilog - Size: 40.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 165 - Forks: 21

giunzz/DDCS336764

FPGA desgin

Language: Verilog - Size: 8.82 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 8 - Forks: 0

WilsonCazarre/6502

FPGA implementation of a 6502 micro-processor

Language: SystemVerilog - Size: 14 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0

iy-kim/DE2-115_FPGA

proficiency of using FPGA with (applying of constraints, Timing Analysis, modelsim Testing, Device Protocal description(with HDL), etc...)

Size: 4.88 KB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

Xilinx/XRT

Run Time for AIE and FPGA based platforms

Language: C++ - Size: 123 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 591 - Forks: 489

fastmachinelearning/hls4ml

Machine learning on FPGAs using HLS

Language: C++ - Size: 257 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,463 - Forks: 448

Ulteavor/FPGA-LCD-MIPI-or-DPI

FPGA LCD MIPI or DPI

Size: 7.22 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

thomas636b/Johnson-HRNG

Johnson-Nyquist Noise Based Multi-Purpose Hardware Random Number Generator

Size: 1.95 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0

chili-chips-ba/openCologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Language: Verilog - Size: 208 MB - Last synced at: 2 days ago - Pushed at: 5 days ago - Stars: 61 - Forks: 6

firesim/firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Language: Scala - Size: 60.5 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 925 - Forks: 236

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.24 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 24 - Forks: 5

lusm554/fromthetransistor

Project dedicated to building a computer system entirely from scratch.

Size: 154 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

tanzimyasr/luna

Self-Hosted Calendar Aggregator and Frontend

Language: Go - Size: 325 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

darklife/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Language: Verilog - Size: 3.94 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2,297 - Forks: 302

ericpearson1313/fpga_life

Conway's game of life FPGA @ 1 million generations per second.

Language: SystemVerilog - Size: 12.6 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

Choaib-ELMADI/risc-v-on-de1-soc-fpga

A simplified RISC-V processor implemented in Verilog and deployed on the DE-1 SoC FPGA board.

Language: Verilog - Size: 24.3 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 5 - Forks: 2

Gabriele-bot/100G-verilog-RoCEv2-lite

TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

Language: Verilog - Size: 18.7 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 12 - Forks: 0

jasonyu1996/anvil

Language: OCaml - Size: 1000 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 4 - Forks: 0

enjoy-digital/litex

Build your hardware, easily!

Language: C - Size: 16.8 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 3,290 - Forks: 615

open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Language: Verilog - Size: 484 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 753 - Forks: 256

enkerewpo/methane

A polyphonic synthesizer built on fpga and esp32

Language: SystemVerilog - Size: 67.5 MB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 1

spcl/dace

DaCe - Data Centric Parallel Programming

Language: Python - Size: 66.4 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 522 - Forks: 135

alonsovazqueztena/Basic_Calculator

A calculator that app that performs mathematical operations on an embedded systems board.

Language: VHDL - Size: 264 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

tommythorn/Reduceron

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

Language: Haskell - Size: 8.62 MB - Last synced at: 4 days ago - Pushed at: 13 days ago - Stars: 432 - Forks: 33