GitHub / VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

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Commits: 1865
Authors: 96
Mean commits per author: 19.43
Development Distribution Score: 0.642
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Topics: asic, fpga, systemverilog-hdl, testbench, unit-testing, universal-verification-methodology, verification, verilog-hdl, vhdl

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