VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

Language: VHDL - Size: 14.1 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 796 - Forks: 285

Rushikesh321/adder

Event-driven tool/library for tailing the Cardano blockchain blockchain, cardano, ouroboros, ouroboros-network, toolbox

Language: Go - Size: 109 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

ab-ff/Multi-Bit-Comparator

Variations of a multi-bit generalized comparator for different area and timing.

Size: 1000 Bytes - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

capopaul/Public-Verilog-Design-Flow-And-Environment

Provide a basic structure to starts a Verilog or Systemverilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)

Language: Python - Size: 27.3 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

vowstar/qsoc

QSoC - Quick System on Chip Studio

Language: C++ - Size: 1.81 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 5 - Forks: 2

Team-gonghack/gonghack-PL

FPGA PL 부분, I2C FSM로직 구현 및 AXI-Lite와 AXI-Stream을 이용해서 DMA구현, AI연산을 DPU로 구현해 AI를 하드웨어로 가속

Language: VHDL - Size: 163 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 1

LSC-Unicamp/processor_ci

Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

Language: SystemVerilog - Size: 1.95 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 12 - Forks: 1

metr0jw/Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA

FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch

Language: Verilog - Size: 396 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 85 - Forks: 6

KapoorAkshit18/vsd-riscv

Advanced Embedded Systems

Language: Verilog - Size: 6.08 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 2 - Forks: 0

AUDIY/Questa_Verification_Tutorials

Examples for the Questa本 (Tentative)

Language: Verilog - Size: 43 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

mirseo/JSilicon

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

Language: SystemVerilog - Size: 1.23 MB - Last synced at: 18 days ago - Pushed at: 28 days ago - Stars: 94 - Forks: 9

ben-marshall/uart

A simple implementation of a UART modem in Verilog.

Language: Verilog - Size: 53.7 KB - Last synced at: 19 days ago - Pushed at: about 4 years ago - Stars: 160 - Forks: 25

Tavakalmastan/Elevator-Control-System

A Verilog HDL project for an Elevator Control System, complete with a Python Tkinter GUI for real-time simulation. 🚀

Language: Verilog - Size: 25.4 KB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0

bangnguyen1144/FPGA-Based-Edge-Detection-with-Salt-and-Pepper-Denoising

FPGA-based edge detection with salt-and-pepper denoising was successfully implemented on the DE10-Standard board, and results were displayed on a VGA display.

Language: Verilog - Size: 46.8 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0

dohuyminhdung/PQC_Dilithium

Language: SystemVerilog - Size: 98.6 KB - Last synced at: 21 days ago - Pushed at: 22 days ago - Stars: 3 - Forks: 0

amitops2103/HDL_bits

Language: Verilog - Size: 58.6 KB - Last synced at: 23 days ago - Pushed at: 24 days ago - Stars: 2 - Forks: 0

sysprog21/vga-nyancat

Hardware-accelerated Nyancat animation on VGA display, implemented in Verilog RTL

Language: C++ - Size: 104 KB - Last synced at: 19 days ago - Pushed at: 29 days ago - Stars: 13 - Forks: 0

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.29 MB - Last synced at: about 2 hours ago - Pushed at: about 4 hours ago - Stars: 340 - Forks: 83

ShankhalikaMallick/RTL_CODING

basic verilog HDL coding

Language: Verilog - Size: 190 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

ShankhalikaMallick/RISC_V

RISC-V CORE DESIGN USING RV32I BASE ISA

Language: Verilog - Size: 14.6 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

Gowtham1729/Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

Language: VHDL - Size: 25 MB - Last synced at: 20 days ago - Pushed at: 6 months ago - Stars: 217 - Forks: 41

Pranav-2045/CORDIC

A synthesizable 16-stage pipelined CORDIC engine in Verilog for high-throughput sine and cosine calculation. 🚀

Language: Verilog - Size: 15.6 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

Michaelvll/RISCV_CPU

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Language: C - Size: 23.5 MB - Last synced at: 23 days ago - Pushed at: almost 6 years ago - Stars: 93 - Forks: 14

periareon/rules_verilog

Bazel rules for Verilog synthesis

Language: Starlark - Size: 1.09 MB - Last synced at: 29 days ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

yasnakateb/PipelinedMIPS

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 75.2 KB - Last synced at: about 1 month ago - Pushed at: about 5 years ago - Stars: 11 - Forks: 0

xunqianxun/liguoqi-rv64-cpu

RISC-V 64 CPU

Language: C++ - Size: 57.6 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 10 - Forks: 2

geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

Language: Verilog - Size: 11.6 MB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 27 - Forks: 4

ninzzd/RISC-V

Language: Verilog - Size: 130 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

scar027/digital-basics

Fundamental verilog codes covering combinational circuits, sequential circuits and finite state machines.

Language: Verilog - Size: 10.7 KB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Ali-975/DV_Training_NCDC

Design Verification (DV) Engineer Training at NCDC, Islamabad — covering C programming, Assembly, RISC-V ISA, SystemVerilog, Computer Architecture, UVM Methodology, and other verification concepts.

Language: Tcl - Size: 201 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Karan-nevage/HDLBits-Complete-Solutions

HDLBits Complete Solutions A repository containing complete solutions for all HDLBits exercises, a platform designed to help learners practice digital hardware design using Verilog. The solutions cover topics ranging from basic Verilog syntax to advanced circuit design challenges, ensuring a smooth learning curve.

Language: Verilog - Size: 49.8 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0

NellyW8/VeriReason

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Language: Python - Size: 277 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 11 - Forks: 3

mauriziotirabassi/ieee754_fpadder

Pipelined 32-bit adder with IEEE754 compliance and special-case handling

Language: VHDL - Size: 13.6 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

vlsienthusiast00x/rv32imc-pipelined-cpu

5-stage pipelined RV32IM core in Verilog.

Language: Verilog - Size: 211 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

PyHDI/veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Language: Python - Size: 11.4 MB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 320 - Forks: 58

omasanori/veriwell 📦

A Verilog (IEEE 1364-1995) simulator

Language: C++ - Size: 3.39 MB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 0

NikhilRout/verilog-dsd

Verilog implementations of fundamental combinational and sequential circuits (with testbenches)

Language: Verilog - Size: 3.97 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

SACHINUR17/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: SystemVerilog - Size: 8.76 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 0

levinh-3105/Matrix-Multiplicator-Verilog

Assignment HDL

Language: Verilog - Size: 24.4 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

Awais-Asghar/FPGA-Based-Smart-Car-Security-System

A Smart Anti-Theft Car Security System implemented on FPGA to detect and prevent unauthorized access. The system uses real-time monitoring and control logic to enhance vehicle safety and response.

Language: Verilog - Size: 17.5 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

yoshinrt/vpp

Verilog HDL preprocessor

Language: Perl - Size: 102 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

JASLemos/RV32IM

A 32 bit RISC-V RV32IM CPU described in Verilog HDL.

Language: VHDL - Size: 29.4 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

JASLemos/Booth-Encoded-Wallace-Tree

A 32 bit Booth Encoded Wallace Tree Multiplier in Verilog HDL.

Language: C - Size: 1.3 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

PyHDI/Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

Language: Python - Size: 701 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 742 - Forks: 203

rao-shreyashree/ddco-verilog

Collection of foundational digital logic modules implemented in Verilog, including gates, adders, multiplexers, demultiplexers, encoders, and decoders. Simulated using Icarus Verilog and visualized with GTKWave for waveform analysis.

Language: Verilog - Size: 39.1 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

xver/icecream_sv

IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.

Language: SystemVerilog - Size: 275 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 0

jchabloz/verisocks

A generic verification interface to Verilog simulators using TCP sockets

Language: C - Size: 668 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 0

SarahMSalah/Down_Counter

This repository contains a Verilog implementation of a 4-bit Down Counter with load, decrement, and zero-detection functionality. It also includes a testbench for verification, along with simulation waveform screenshots that demonstrate correct operation.

Language: Verilog - Size: 173 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

ErickMaRi/HDL-Bitnet-1.58

Transformer Bitnet en Verilog

Language: Verilog - Size: 4 MB - Last synced at: 16 days ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 2

PranavR03/mips-pipelined-cpu

A 5-stage pipelined MIPS processor in Verilog

Language: Verilog - Size: 16.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

AISeQLab/Level_0_KV260_FPGA

A sample FPGA project on KV260

Language: C - Size: 74.4 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 28 - Forks: 5

underthenightsky/7_Segment_Display

This project implements and simulates a 7-segment display decoder in Verilog. The decoder takes a 4-bit binary input (representing values 0–15) and generates the corresponding 7-bit output pattern to drive a 7-segment display.

Language: Verilog - Size: 2.93 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

SarahMSalah/Up_Dn_Counter

This repository contains a 5-bit synchronous up/down counter written in Verilog. The counter can load an initial value, increment, or decrement depending on control signals. It also provides flags to indicate when the counter reaches its maximum (31) or minimum (0) value.

Language: Verilog - Size: 2.93 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Unicamp-Odhin/DRAM_Wrapper

A Lite DRAM helper maked in System Verilog HDL.

Language: Verilog - Size: 298 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

atrejojr/Projects

Projects made while at BU

Language: JavaScript - Size: 6.42 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

wdevore/A09-Softcore-Processor

An FPGA softcore processor for a corresponding video series.

Language: Verilog - Size: 10.2 MB - Last synced at: 28 days ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 3

vlsienthusiast00x/rv32im-single-cycle-cpu

Verilog-based single-cycle CPU implementing the RV32IM instruction set. Supports integer and multiplication/division instructions with modular design, ALU, control unit, and UART-based debugging.

Language: Verilog - Size: 212 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 3 - Forks: 1

fermarsan/veri2sim

This is a simple Verilog to SimulIDE block converter written in Python using the PLY module.

Language: Python - Size: 246 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 1

sainathyarrabhumi-crypto/y1str

Language: SystemVerilog - Size: 45.9 KB - Last synced at: about 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

Weiyet/RTLStructLib

RTL data structure

Language: SystemVerilog - Size: 564 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 52 - Forks: 4

Lucas-Sousa-S/LD

Repository of lists of resolved issues

Language: Verilog - Size: 203 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

NNgen/nngen

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Language: Python - Size: 1.41 MB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 355 - Forks: 49

sudhamshu091/32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

Language: Verilog - Size: 12.6 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 4 - Forks: 2

Sanugiw/FPGA

UA UART communication module using Verilog on a DE0-Nano FPGA with real-time serial data transfer, and verified functionality with a custom test bench.

Size: 3.49 MB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

galihru/logicsim

The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin

Language: JavaScript - Size: 423 KB - Last synced at: 28 days ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0

RISC-KC/basic_rv32s

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

Language: Verilog - Size: 79.1 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 5 - Forks: 0

Manthan-cpu/IITISOC-solution

This project implements an 8-bit RISC processor in Verilog with a 5-stage pipeline (Fetch, Decode, Execute, Memory, Write Back). It supports a custom instruction set and handles data and control hazards using forwarding, stalling, and flushing mechanisms.

Language: Verilog - Size: 452 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

ADHIL48/Verilog-HDL-Project-Hub

This repository contains Verilog HDL projects covering arithmetic units, memory blocks, FSMs, and protocols. It’s perfect for VLSI and FPGA learners to practice and understand digital design through synthesizable modules.

Language: Verilog - Size: 14.9 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

michaelehab/AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Language: Verilog - Size: 8.73 MB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 105 - Forks: 26

SUHANI102003/VERILOG-SEQUENTIAL_CIRCUITS

Verilog codes for sequential circuits

Language: Verilog - Size: 1.83 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

nishit0072e/RTL-to-GDSII

Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation

Language: C++ - Size: 7.92 MB - Last synced at: 2 months ago - Pushed at: 4 months ago - Stars: 11 - Forks: 2

maazm007/vsdsquadron-mini-internship

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

Language: C - Size: 102 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 28 - Forks: 15

vlsienthusiast00x/ALU_74181

A simulation of the classic 4-bit 74181 Arithmetic Logic Unit (ALU), built from scratch in Verilog.

Language: Verilog - Size: 19.5 KB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

SayantanMandal2000/electronic-voting-machine-verilog

🚀 RTL design and testbench implementation of a Digital Electronic Voting Machine (EVM) using Verilog HDL. The EVM is modeled with a modular, FSM-based architecture suitable for FPGA or ASIC prototyping and educational use.

Language: Verilog - Size: 1.84 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

noescine/GCPU_implementation-

SARABI2 es una unidad de procesamiento de propósito general basada en la arquitectura RISC monociclo diseñada desde cero para optimizar la eficiencia energética y el uso del silicio. Implementa un conjunto de instrucciones personalizado inspirado en RV32I, con operaciones combinacionales, aritméticas, lógicas y de control de flujo.

Language: Verilog - Size: 34.3 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Tan184/master-slave-bus-address-router

A Verilog-based bus routing module that connects one master to multiple slaves using address-based decoding logic. Includes a modular SystemVerilog testbench (driver, monitor, scoreboard, etc.) to verify correct routing and functionality across defined address ranges.

Language: SystemVerilog - Size: 30.3 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

kolirigved/VisionForge

EEA Winter Project 2023-24

Language: Jupyter Notebook - Size: 620 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

SayantanMandal2000/rtl-ahb-to-apb-bridge

🚀 Synthesizable Verilog RTL implementation of an AMBA AHB-to-APB protocol bridge using a finite state machine (FSM).Designed for integration in SoC and IP subsystems that interface high-performance AHB masters with low-power APB peripherals.

Language: Verilog - Size: 217 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

SayantanMandal2000/rtl-fifo-designs

🚀 RTL design of synchronous and dual-clock asynchronous FIFO buffers in Verilog, featuring flow control, pointer logic, and waveform-based validation.

Language: Verilog - Size: 173 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Sajitha-Madugalle/32-bit-Floating-Point-Arithmetic-Unit

The repository contains the source files regarding an ALU design and FPGA implimentation Project.

Language: Verilog - Size: 506 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

Raghad-alju/fsm-sequence-detector

Implement a 3-bit sequence detector for `110` using a Mealy FSM in Cadence Virtuoso. Built with TSPC D flip-flops for optimal performance. 🛠️💻

Size: 808 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

jElhamm/Verilog-HDL-Codes-Collection

"Repository containing a collection of Verilog code modules and test bench for digital design projects. "

Language: Verilog - Size: 387 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

AlphaLyrae0/Emacs_Verilog_Mode_Examples

Examples of auto signal connection with Emacs verilog-mode

Language: SystemVerilog - Size: 18.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

EswarAdithya011/100DaysRTLChallenge

This repo contains implementation of digital circuits and some projects related to them in Verilog language at different abstraction levels..

Language: Verilog - Size: 10.2 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

donghch/naive-4004

Simple Intel 4004 Processor Implementation

Language: Verilog - Size: 18.6 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Thejas2006/symbol-timing-recovery-circuit_gardner

An str circuit for timing synchronisation.

Language: Verilog - Size: 34.2 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Elihelmo/Kintex-7-MIPI-DSI-6.9-inch-LCD

This repository contains a Verilog-based HDL design for driving a 6.9-inch MIPI DSI LCD using the Kintex-7 FPGA. Explore the project to simplify your display initialization without relying on complex IPs. 🖥️🌟

Size: 2.14 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

RuSys/Verugent

Verilog generation tool written in Rust

Language: Rust - Size: 77.1 KB - Last synced at: 22 days ago - Pushed at: over 2 years ago - Stars: 59 - Forks: 5

ADHIL48/Verilog-HDLBits-Solutions

This is a repository containing solutions to the problem statements given in Verilog HDL Bits website.

Language: Verilog - Size: 0 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

AmitPatel2327/5-stage-Pipelined-MIPS32-Processor-Design

A 32 bit RISC processor designed using Verilog. Implementing some of the basic ALU functions i.e. ADD, SUB, MUL, AND, OR, ADDI , SUBI, SLTI, LW, SW, BEQZ, BNEQZ etc.

Language: Verilog - Size: 3.91 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Thejas2006/symbol-timing-recovery-circuit_S_D

An str circuit for timing synchronisation.

Language: Verilog - Size: 11.7 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

snbk001/Verilog-Design-Examples

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier

Language: Verilog - Size: 126 KB - Last synced at: 4 months ago - Pushed at: almost 2 years ago - Stars: 132 - Forks: 23

theveryhim/FFT-Display-using-Zynq7000

Signal processing using Zynq7000 Board(AX7010)

Language: MATLAB - Size: 212 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

asrdav/CS322-Architecture-Lab

Contains solutions of Architecture lab CS321/CS322 (IIT Patna) assignments using Verilog,etc.

Language: Assembly - Size: 2.36 MB - Last synced at: 3 months ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 3

SKpro-glitch/Multi-Bit-Comparator

Variations of a multi-bit generalized magnitude comparator for different area and timing.

Language: D - Size: 275 KB - Last synced at: 4 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

sakethakella/FFT_DIT_8point

8-point FFT calculator

Language: Verilog - Size: 4.88 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

JN513/Grande-Risco-5

Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.

Language: Verilog - Size: 1.15 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 7 - Forks: 0

anup209th/Go_lemo_go

Lemmings FSM game on 8051 with LEDs & buttons

Size: 0 Bytes - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

Tanvir-Mahamood/Circuit-Design

Circuit simulation and HDL

Language: Verilog - Size: 14.4 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

SemenovMD/eth-sv

Ethernet SystemVerilog UDP/IP ARP ICMP AXI Stream

Language: SystemVerilog - Size: 1.02 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0