GitHub topics: systemverilog | Ecosyste.ms: Repos

siliscale/Tiny-Vedas

A simple RISC-V RV32IM Core for education

Language: SystemVerilog - Size: 5.5 MB - Last synced at: about 2 hours ago - Pushed at: about 3 hours ago - Stars: 15 - Forks: 1

xver/svdb_gateway

SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.

Language: Python - Size: 479 KB - Last synced at: about 8 hours ago - Pushed at: about 9 hours ago - Stars: 1 - Forks: 0

taneroksuz/cpu-medium

6-stage in-order dual-issue superscalar risc-v cpu with floating point unit

Language: SystemVerilog - Size: 711 KB - Last synced at: about 11 hours ago - Pushed at: about 12 hours ago - Stars: 13 - Forks: 5

taneroksuz/cpu-low

2-stage in-order scalar risc-v cpu

Language: SystemVerilog - Size: 591 KB - Last synced at: about 11 hours ago - Pushed at: about 12 hours ago - Stars: 4 - Forks: 3

amitops2103/verilog-space-commander

An intelligent, Verilog-based AI fleet controller for the Makerchip ASIC Design Showdown 2025. stellar-strike-ai combines predictive targeting, adaptive defense, and boundary-safe maneuvering to dominate in real-time space combat. Designed using TL-Verilog and fully compatible with the Makerchip simulation environment.

Language: SystemVerilog - Size: 12.7 KB - Last synced at: about 14 hours ago - Pushed at: about 15 hours ago - Stars: 0 - Forks: 0

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

panastasiadis/embedded-systems-projects

A collection of educational embedded systems projects using HLS, Arduino, and Verilog — developed for the course Embedded Systems Programming in Edge Environments.

Language: Jupyter Notebook - Size: 0 Bytes - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.28 MB - Last synced at: 1 day ago - Pushed at: 3 days ago - Stars: 323 - Forks: 81

semify-eda/go.debug

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

Language: SystemVerilog - Size: 11.9 MB - Last synced at: about 19 hours ago - Pushed at: over 3 years ago - Stars: 11 - Forks: 3

Nambers/MIPS64

[WIP] 5-stage pipeline MIPS64 SoC implementation with peripheral components, simulated with verilator

Language: SystemVerilog - Size: 896 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Language: SystemVerilog - Size: 106 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 113 - Forks: 52

pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language: SystemVerilog - Size: 9.43 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,308 - Forks: 298

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 19.8 MB - Last synced at: 2 days ago - Pushed at: 4 days ago - Stars: 1,509 - Forks: 162

realise-lab/hwpq

Hardware Priority Queue Library

Language: SystemVerilog - Size: 181 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 1

dalance/svlint

SystemVerilog linter

Language: Rust - Size: 4.14 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 348 - Forks: 42

Intuity/packtype

Packed data structure specifications for multi-language hardware projects.

Language: Python - Size: 240 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 7 - Forks: 1

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 1

Ryoga-exe/cojt-hw

University of Tsukuba COJT Embedded Systems OJT Hardware Course assignments

Language: SystemVerilog - Size: 44.9 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

cyril0124/verilua

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Language: Lua - Size: 3.23 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 4 - Forks: 0

tmeissner/formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

Language: VHDL - Size: 205 KB - Last synced at: 2 days ago - Pushed at: over 1 year ago - Stars: 42 - Forks: 7

HEP-SoC/SoCMake

CMake based hardware build system

Language: CMake - Size: 6.07 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 27 - Forks: 3

openhwgroup/core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Language: SystemVerilog - Size: 35.2 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 177 - Forks: 62

dau-dev/verilator-python

Python/PyPI wrapper for Verilator

Language: Python - Size: 62.5 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 0

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.25 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 26 - Forks: 5

MikePopoloski/slang

SystemVerilog compiler and language services

Language: C++ - Size: 31.4 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 769 - Forks: 158

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language: Verilog - Size: 30.8 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 267 - Forks: 69

MatthieuMichon/zcu106-silent-fan

Minimalist design enabling low-noise fan operation

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 1,173 - Forks: 128

Ghonimo/Formal-Verification-With-VC-Formal--Tutorials-and-Examples

This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our goal is to help both beginners and experienced users understand the principles of formal verification and how to apply them effectively using VC Formal.

Size: 96.8 MB - Last synced at: 6 days ago - Pushed at: over 1 year ago - Stars: 31 - Forks: 2

Sibakumarpanda/UP_Counter_4bit_Verification_with_UVM

UP_Counter_4bit_Verification_with_UVM

Language: SystemVerilog - Size: 175 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 0

BlueTheDuck/riscv-sv

RV32I implementation written in SystemVerilog

Language: SystemVerilog - Size: 174 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

MPSU/APS

Методические материалы по разработке процессора архитектуры RISC-V

Language: SystemVerilog - Size: 115 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 202 - Forks: 57

saadelahii/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1.01 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

chili-chips-ba/openPCIE

Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the Host side! Our project roots for Root Complex in 4 ways: 1) openRTL; 2) openBFM with unique sim setup, better performing than vendor TB; 3) openSoftware stack; 4) one-of-the kind openBackplane

Size: 60.9 MB - Last synced at: 4 days ago - Pushed at: 21 days ago - Stars: 13 - Forks: 0

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 78.4 MB - Last synced at: 7 days ago - Pushed at: 12 days ago - Stars: 723 - Forks: 38

WangXuan95/FPGA-CAN

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

Language: Verilog - Size: 416 KB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 272 - Forks: 82

SKpro-glitch/Parallel_Multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 2 - Forks: 0

chipsalliance/UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 4.36 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 219 - Forks: 43

chili-chips-ba/openCologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Language: Verilog - Size: 207 MB - Last synced at: 8 days ago - Pushed at: 30 days ago - Stars: 65 - Forks: 7

chili-chips-ba/openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

Language: SystemVerilog - Size: 276 MB - Last synced at: 8 days ago - Pushed at: 10 days ago - Stars: 49 - Forks: 10

Davidls10/riscv-pipelined-sv

Simple RISC-V Pipelined processor implemented on SystemVerilog.

Language: SystemVerilog - Size: 27.3 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 5 - Forks: 0

WangXuan95/FPGA-FOC

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Language: Verilog - Size: 666 KB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 700 - Forks: 208

pkpkp456/Learn_System_Verilog

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

Language: SystemVerilog - Size: 10.3 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

dalance/svls

SystemVerilog language server

Language: Rust - Size: 810 KB - Last synced at: 8 days ago - Pushed at: 16 days ago - Stars: 513 - Forks: 31

WangXuan95/FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Language: Verilog - Size: 75.2 KB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 189 - Forks: 33

paolopedroso/riscvectorcore

5-Stage RISC-V Processor with Verification Environment

Language: SystemVerilog - Size: 21.8 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 1 - Forks: 0

chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 841 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 395 - Forks: 76

Lamagraph/intro-to-fpga-with-clash

Materials to start FPGA programming with SystemVerilog and Clash

Language: SystemVerilog - Size: 1.09 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 2

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 12.2 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 327 - Forks: 82

CharanK-glitch/RV32I

Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.

Language: Verilog - Size: 243 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 2 - Forks: 1

BrianHGinc/BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Language: SystemVerilog - Size: 9.94 MB - Last synced at: 7 days ago - Pushed at: about 1 year ago - Stars: 79 - Forks: 34

Intuity/forastero

Making cocotb testbenches that bit easier

Language: Python - Size: 252 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 29 - Forks: 1

WangXuan95/FPGA-NFC

An FPGA-based NFC (RFID) reader with a simple circuit rather than RFID chips. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。

Language: Verilog - Size: 500 KB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 127 - Forks: 26

Nic30/hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

Language: C++ - Size: 14.4 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 298 - Forks: 73

Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Language: Python - Size: 19.3 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 212 - Forks: 28

Nic30/hdlConvertorAst

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Language: Python - Size: 781 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 36 - Forks: 9

kaushalmodi/nim-systemverilog-dpic

Using Nim to interface with SystemVerilog test benches via DPI-C

Language: SystemVerilog - Size: 2.85 MB - Last synced at: 6 days ago - Pushed at: about 1 month ago - Stars: 31 - Forks: 4

Kingfish404/ysyx-workbench

OoO 6-stage RISC-V core. Verify: riscv-arch-test. Difftest: Spike & NEMU (boot Linux).

Language: C - Size: 5.85 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 4 - Forks: 0

kamberasaf/divide-by-3-clock-divider

SystemVerilog divide-by-3 clock divider with 50% duty cycle using dual counter architecture

Language: SystemVerilog - Size: 267 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0

Madhu-Krishnan-A-P/pattern-detector

SystemVerilog implementations of a 101 pattern detector using both structural and behavioral modeling styles. Includes separate testbenches for each implementation. Designed for detecting overlapping 101 patterns in a serial bitstream, useful for learning FSM design and simulation in digital systems.

Language: SystemVerilog - Size: 190 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

Madhu-Krishnan-A-P/binary-gray-converter

SystemVerilog implementation of a Binary to Gray Code Converter in both structural and behavioral styles. Includes a simple testbench for verification. Useful for digital design learners and FPGA developers.

Language: SystemVerilog - Size: 222 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Language: C++ - Size: 12.7 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 1,554 - Forks: 238

jeras/rp32

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

Language: SystemVerilog - Size: 1.13 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 18 - Forks: 4

RDSik/axis-uart

AXI-Stream UART module

Language: SystemVerilog - Size: 313 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1 - Forks: 0

Karan-nevage/HDLBits-Complete-Solutions

HDLBits Complete Solutions A repository containing complete solutions for all HDLBits exercises, a platform designed to help learners practice digital hardware design using Verilog. The solutions cover topics ranging from basic Verilog syntax to advanced circuit design challenges, ensuring a smooth learning curve.

Language: Verilog - Size: 6.84 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 0 - Forks: 0

sifferman/labs-with-cva6

Advanced Architecture Labs with CVA6

Language: SystemVerilog - Size: 311 KB - Last synced at: 1 day ago - Pushed at: over 1 year ago - Stars: 62 - Forks: 26

shinolab/autd3-firmware

Language: SystemVerilog - Size: 839 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 1 - Forks: 0

PyFPGA/HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Language: Python - Size: 5.15 MB - Last synced at: 14 days ago - Pushed at: 4 months ago - Stars: 25 - Forks: 2

chaseruskin/verb

An approachable testing framework for digital hardware

Language: Python - Size: 1.99 MB - Last synced at: 4 days ago - Pushed at: 29 days ago - Stars: 4 - Forks: 0

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.05 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 695 - Forks: 203

intel/rohd-hcl

A hardware component library developed with ROHD.

Language: Dart - Size: 28.5 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 94 - Forks: 29

SystemRDL/PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Language: Python - Size: 918 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 66 - Forks: 47

mikeroyal/Verilog-SystemVerilog-Guide

Verilog/SystemVerilog Guide

Language: SystemVerilog - Size: 19.5 KB - Last synced at: 3 days ago - Pushed at: over 1 year ago - Stars: 67 - Forks: 9

chaseruskin/orbit

Package manager and build system for VHDL, Verilog, and SystemVerilog

Language: Rust - Size: 59.6 MB - Last synced at: 4 days ago - Pushed at: 24 days ago - Stars: 47 - Forks: 2

pulp-platform/carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Language: Tcl - Size: 6.3 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 104 - Forks: 21

jeras/TCB

Tightly Coupled Bus, low complexity, high performance system bus.

Language: SystemVerilog - Size: 975 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 4 - Forks: 0

WangXuan95/FPGA-SATA-HBA

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

Language: SystemVerilog - Size: 5.06 MB - Last synced at: 7 days ago - Pushed at: almost 2 years ago - Stars: 105 - Forks: 35

loykylewong/FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Language: Scala - Size: 2.95 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 131 - Forks: 30

SACHINUR17/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Verilog - Size: 134 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 1 - Forks: 0

HANANDA1/FPGA-Based-Smart-Car-Security-System

FPGA-Based Smart Car Security System is a robust solution for protecting high-end vehicles like Porsche. It uses Verilog and SystemVerilog to detect unauthorized access and disable the fuel pump, ensuring your car remains secure. 🛠️🚗

Language: Verilog - Size: 9.27 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 0 - Forks: 0

cristian-mattarei/CoSA

CoreIR Symbolic Analyzer

Language: Python - Size: 7.98 MB - Last synced at: 6 days ago - Pushed at: over 4 years ago - Stars: 73 - Forks: 18

VLSI-r/HDL-Projects

My_HDL_Projects!

Size: 1.28 MB - Last synced at: 18 days ago - Pushed at: 19 days ago - Stars: 1 - Forks: 0

TerosTechnology/vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Language: VHDL - Size: 150 MB - Last synced at: 18 days ago - Pushed at: 3 months ago - Stars: 619 - Forks: 53

agalimberti/NoCRouter

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

Language: SystemVerilog - Size: 659 KB - Last synced at: 18 days ago - Pushed at: over 7 years ago - Stars: 126 - Forks: 41

Awais-Asghar/FPGA-Based-Smart-Car-Security-System

A Smart Anti-Theft Car Security System implemented on FPGA to detect and prevent unauthorized access. The system uses real-time monitoring and control logic to enhance vehicle safety and response.

Language: Verilog - Size: 9.35 MB - Last synced at: 20 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0

Madhu-Krishnan-A-P/4bitadder

Verilog implementations of a 4-bit adder using behavioral, dataflow, and structural modeling styles, along with corresponding testbenches and block diagrams. This project demonstrates the design and simulation of digital adders as part of an academic lab experiment.

Language: Verilog - Size: 1.26 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0