GoProMcDonald/Async-Fifo-Cdc-Uvm-Verification

UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

Language: SystemVerilog - Size: 19.5 KB - Last synced at: about 3 hours ago - Pushed at: about 4 hours ago - Stars: 0 - Forks: 0

pezy-computing/pzbcm

Basic Common Modules

Language: SystemVerilog - Size: 362 KB - Last synced at: about 5 hours ago - Pushed at: about 7 hours ago - Stars: 44 - Forks: 8

MikePopoloski/slang

SystemVerilog compiler and language services

Language: C++ - Size: 31.7 MB - Last synced at: about 7 hours ago - Pushed at: about 9 hours ago - Stars: 816 - Forks: 167

Lamagraph/intro-to-fpga-with-clash

Materials to start FPGA programming with SystemVerilog and Clash

Language: SystemVerilog - Size: 2.26 MB - Last synced at: about 20 hours ago - Pushed at: about 22 hours ago - Stars: 1 - Forks: 2

SUHANI102003/50-days-of-Verification

This repo contains the verification basics of System verilog and UVM

Language: SystemVerilog - Size: 3 MB - Last synced at: about 23 hours ago - Pushed at: about 23 hours ago - Stars: 0 - Forks: 0

midimaster21b/amba-interfaces

A few quick interfaces for AMBA standards

Language: VHDL - Size: 62.5 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

GoProMcDonald/AXI4-Interconnect-Fabric-Verification-with-UVM

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

Language: SystemVerilog - Size: 44.9 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 2 - Forks: 0

sagikimhi/nice

A nice-to-have SystemVerilog-UVM verification kit

Language: SystemVerilog - Size: 14.5 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 1 - Forks: 0

cyril0124/verilua

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Language: Lua - Size: 3.73 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 5 - Forks: 0

MPSU/APS

Методические материалы по разработке процессора архитектуры RISC-V

Language: SystemVerilog - Size: 117 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 255 - Forks: 63

saadelahii/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1.01 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 1

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 1

topologicalhurt/Thesis

Fpga thesis project. An intelligent hardware scheduling algorithm focused on common signal chains.

Language: Python - Size: 130 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 1

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 12.5 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 338 - Forks: 83

ollycassidy13/MAX

A parameterizable SystemVerilog module for finding the maximum value and its index from chunked input data.

Language: SystemVerilog - Size: 5.86 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

vyges/vyges-ip-template

🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

Language: Python - Size: 300 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.07 MB - Last synced at: 2 days ago - Pushed at: 28 days ago - Stars: 707 - Forks: 210

chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Language: C++ - Size: 12.8 MB - Last synced at: 3 days ago - Pushed at: 8 days ago - Stars: 1,612 - Forks: 248

chili-chips-ba/openCologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Language: Verilog - Size: 296 MB - Last synced at: 3 days ago - Pushed at: 11 days ago - Stars: 67 - Forks: 7

BlueTheDuck/riscv-sv

RV32I implementation written in SystemVerilog

Language: SystemVerilog - Size: 226 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

GoProMcDonald/PCIe-Gen3-Endpoint-Subsystem-Verification

UVM + DPI-C reference model for PCIe Gen3 endpoint (transaction layer)

Language: SystemVerilog - Size: 226 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

Unicamp-Odhin/DRAM_Wrapper

A Lite DRAM helper maked in System Verilog HDL.

Language: Verilog - Size: 298 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

suzizecat/diplomat-vscode

System verilog support VS Code Extension

Language: TypeScript - Size: 250 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 5 - Forks: 1

chili-chips-ba/openPCIE

Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the Host side! Our project roots for Root Complex in 4 ways: 1) openRTL; 2) openBFM with unique sim setup, better performing than vendor TB; 3) openSoftware stack; 4) one-of-the kind openBackplane

Language: HTML - Size: 138 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 14 - Forks: 2

AlphaLyrae0/UVM_DPI_Example

Example of DPI-C usage in UVM with Vivado simulator (xsim) and Altair (Metrics) DSim

Language: SystemVerilog - Size: 45.9 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 0

CT7-labs/argon-cpu

Custom CPU written in Verilog

Language: SystemVerilog - Size: 159 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 80.3 MB - Last synced at: 5 days ago - Pushed at: 7 days ago - Stars: 761 - Forks: 43

siliscale/Tiny-Vedas

A highly-configurable RISC-V Core

Language: SystemVerilog - Size: 5.34 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 24 - Forks: 2

F1-uxy/riscv

Language: SystemVerilog - Size: 38.4 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 1,194 - Forks: 129

pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Language: Python - Size: 5.36 MB - Last synced at: 4 days ago - Pushed at: 4 months ago - Stars: 424 - Forks: 55

pkpkp456/Learn_System_Verilog

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

Language: Jupyter Notebook - Size: 24.1 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

Intuity/packtype

Packed data structure specifications for multi-language hardware projects.

Language: Python - Size: 340 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 8 - Forks: 1

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.34 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 334 - Forks: 82

pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language: SystemVerilog - Size: 9.67 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 1,350 - Forks: 304

Kingfish404/ysyx-workbench

OoO 6-stage CPU (rv32imac_zicntr_zicsr_zifencei).

Language: C - Size: 6.02 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 4 - Forks: 1

mit41301/Z80_CYCLONE_IV_EP4CE6E22C8

Simple Z80 CPU with inbuilt 8kB ROM and 4kB RAM using T80 core. Operating at 50MHz clock with Tx, Rx and reset. UART terminal at 115200 baud. One 8 bit output port at 145 connected to LEDs.

Language: BASIC - Size: 161 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

ericpearson1313/fpga_life

Conway's game of life FPGA at 1 million generations per second. UPDATE: 10 generations x 256 cells gives 6 million gen/sec, and finally 11x256 gives us 6.6 MHz gen rate using 100% of a 10M25

Language: SystemVerilog - Size: 15.2 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

cong2738/FlagGame

FlagGame : ISP_RTL_Design(HarmanSA_June_TeamPJ)

Language: SystemVerilog - Size: 71.3 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 3

pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Language: SystemVerilog - Size: 106 MB - Last synced at: 6 days ago - Pushed at: 29 days ago - Stars: 132 - Forks: 66

Karan-nevage/HDLBits-Complete-Solutions

HDLBits Complete Solutions A repository containing complete solutions for all HDLBits exercises, a platform designed to help learners practice digital hardware design using Verilog. The solutions cover topics ranging from basic Verilog syntax to advanced circuit design challenges, ensuring a smooth learning curve.

Language: Verilog - Size: 46.9 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

Matthew-Otto/RTL-IP

Common SystemVerilog modules I use in my FPGA projects

Language: SystemVerilog - Size: 2.07 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

aliadelmahdi/Design-and-Verification-of-AMPA-AXI-UVM

AMBA AXI4 design & verification flow in SystemVerilog with UVM 1.2. Includes master/slave RTL & golden models, assertions, functional & code coverage, FSMs, active master & passive slave agents, cross-platform run scripts, and waveform/report generation for protocol-compliant verification.

Language: SystemVerilog - Size: 4.71 MB - Last synced at: 3 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.27 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 32 - Forks: 5

sainathyarrabhumi-crypto/y1str

Language: SystemVerilog - Size: 45.9 KB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

WAVECHIP/cocotb-tutorial

Getting started with cocotb

Language: Python - Size: 12.7 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 1 - Forks: 0

Unicamp-Odhin/GPIO_Peripheral

GPIO Peripheral written in SystemVerilog HDL

Language: SystemVerilog - Size: 9.77 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 1 - Forks: 0

Unicamp-Odhin/I2C-Master

I2C Master Peripheral written in System Verilog HDL

Language: Tcl - Size: 57.6 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0

rggen/rggen-systemverilog

SystemVerilog RTL and UVM RAL model generators for RgGen

Language: Ruby - Size: 725 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 14 - Forks: 1

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 19.9 MB - Last synced at: 6 days ago - Pushed at: 10 days ago - Stars: 1,526 - Forks: 162

Rushi03/logic-design

Learning digital logic design and design verification using SystemVerilog.

Language: SystemVerilog - Size: 4.46 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

midimaster21b/rtl-core-library

A set of common RTL cores that I've developed over time and organized into a FuseSoC library.

Size: 30.3 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 8 - Forks: 1

vyges/full-adder-ip

A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz

Language: Python - Size: 260 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

vyges/uart-controller

A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.

Language: SystemVerilog - Size: 275 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

tymonx/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 57.6 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 5 - Forks: 1

DhruvDes/FPGA-ACC-MAC

4×4 8-bit matrix multiplication hardware accelerator using a systolic array, with a Python driver for the Basys 3 FPGA and a systolic array UVC using UVM.

Language: SystemVerilog - Size: 5.63 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

chili-chips-ba/openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

Language: SystemVerilog - Size: 276 MB - Last synced at: 3 days ago - Pushed at: about 1 month ago - Stars: 58 - Forks: 14

mikeroyal/Verilog-SystemVerilog-Guide

Verilog/SystemVerilog Guide

Language: SystemVerilog - Size: 19.5 KB - Last synced at: 12 days ago - Pushed at: over 1 year ago - Stars: 70 - Forks: 9

loykylewong/FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Language: Scala - Size: 3.09 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 130 - Forks: 30

SystemRDL/PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Language: Python - Size: 935 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 71 - Forks: 48

SystemRDL/PeakRDL

Control and status register code generator toolchain

Language: Python - Size: 143 KB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 142 - Forks: 30

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language: Verilog - Size: 42.5 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 275 - Forks: 74

intel/rohd-hcl

A hardware component library developed with ROHD.

Language: Dart - Size: 39.7 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 100 - Forks: 32

openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Language: Assembly - Size: 112 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 575 - Forks: 251

suryaturaga3142/chipdev-verilog

View my answers to some HDL questions listed for practice on chipdev. I prefer it to HDLBits, but I might add a couple things from there ;)

Language: SystemVerilog - Size: 15.6 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

StuDenTMNF/FullAdder32

В данном репозитории будет рассказано о 32-битном сумматоре с последовательным переносом.

Language: SystemVerilog - Size: 163 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

Unicamp-Odhin/FPGA_101

Starting in the world of FPGAs!!!!!

Language: Tcl - Size: 18.6 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 1 - Forks: 0

HEP-SoC/SoCMake

CMake based hardware build system

Language: CMake - Size: 6.14 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 30 - Forks: 3

RDSik/axis-modules

Some AXI-Stream modules

Language: SystemVerilog - Size: 520 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

oddball/ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Language: Python - Size: 4.22 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 63 - Forks: 21

mauroxf/sv-mini-projects

AI generated SystemVerilog problems I solved during my learning process

Language: SystemVerilog - Size: 121 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 1 - Forks: 0

trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Language: SystemVerilog - Size: 20.4 MB - Last synced at: 3 days ago - Pushed at: about 5 years ago - Stars: 604 - Forks: 102

dalance/svls

SystemVerilog language server

Language: Rust - Size: 891 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 522 - Forks: 31

heyfey/sv-pathfinder

VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

Language: TypeScript - Size: 7.21 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 1 - Forks: 0

Sanugiw/FPGA

UA UART communication module using Verilog on a DE0-Nano FPGA with real-time serial data transfer, and verified functionality with a custom test bench.

Size: 3.49 MB - Last synced at: 7 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Unicamp-Odhin/FPGA_VGA_Workshop

Este projeto tem como objetivo principal o desenvolvimento de um controlador VGA utilizando FPGA (Field-Programmable Gate Array) e linguagem de descrição de hardware (HDL).

Language: Tcl - Size: 1.11 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 2 - Forks: 0

rggen/rggen

Code generation tool for control and status registers

Language: Ruby - Size: 515 KB - Last synced at: 16 days ago - Pushed at: about 1 month ago - Stars: 412 - Forks: 49

AxC1271/Pixel-Gate

This project explores the implementation and applications of neural networks using single layer perceptrons in conjunction with image processing.

Language: Python - Size: 47.9 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 1 - Forks: 0

opendv360/verification-diagrams

This collection of verification diagrams is created to help educators, students, and engineers visualize complex hardware verification concepts. These illustrations transform complex concepts into understandable visuals.

Size: 18 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 1 - Forks: 0

WangXuan95/FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Language: Verilog - Size: 75.2 KB - Last synced at: 9 days ago - Pushed at: almost 2 years ago - Stars: 200 - Forks: 35

pengusystems/kandooma

FPGA Samples by Pengu Systems

Size: 1.27 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 0 - Forks: 0

dau-dev/verilator-python

Python/PyPI wrapper for Verilator

Language: Python - Size: 89.8 KB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 3 - Forks: 0

pulp-platform/astral Fork of pulp-platform/carfield

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

Language: Tcl - Size: 93.6 MB - Last synced at: 17 days ago - Pushed at: 18 days ago - Stars: 10 - Forks: 4

mediaic/Crash_Course_for_New_Members

Deep Learning & VLSI Crash Course for New Members

Size: 72.3 KB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 40 - Forks: 7

feipenghhq/UART_controller

A simple UART Controller written in SystemVerilog

Language: Python - Size: 67.4 KB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0

Karan-nevage/SystemVerilog-Pattern-Generation-Interview-Questions

A focused collection of SystemVerilog pattern generation problems tailored for VLSI interview preparation. Includes simulation-ready solutions, visual outputs, and modular code to help freshers and professionals sharpen their coding skills and ace technical rounds.

Language: SystemVerilog - Size: 11.7 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 0 - Forks: 0

trivialmips/TrivialMIPS

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

Language: SystemVerilog - Size: 84.3 MB - Last synced at: 3 days ago - Pushed at: over 6 years ago - Stars: 107 - Forks: 35

veripool/verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

Language: SystemVerilog - Size: 2.73 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 272 - Forks: 97

JacobPease/emacsprime

Custom Emacs config with Deus Ex Human Revolution theme.

Language: Emacs Lisp - Size: 667 KB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 0 - Forks: 0

suzizecat/slang-lsp-tools

Tools based upon slang for language server purpose

Language: C++ - Size: 325 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 15 - Forks: 2

xver/svdb_gateway

SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.

Language: Python - Size: 546 KB - Last synced at: 22 days ago - Pushed at: 23 days ago - Stars: 3 - Forks: 1

DMoore12/sv-sim

A simple SystemVerilog simulation tool written in rust

Language: Rust - Size: 837 KB - Last synced at: 9 days ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

Nambers/0dMIPS

[WIP] in-order 5-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator

Language: C++ - Size: 3.14 MB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

Unicamp-Odhin/MFCC_Core

MFCC Core written in SystemVerilog

Language: C - Size: 900 KB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 2 - Forks: 0

Harry-Chen/fpga-virtual-console

VT220-compatible console on Cyclone IV EP4CE55F23I7

Language: SystemVerilog - Size: 4.21 MB - Last synced at: 3 days ago - Pushed at: about 7 years ago - Stars: 43 - Forks: 9

vyges/programmable-adc

Programmable ADC IP with Cadence PDK support, featuring behavioral models, comprehensive testbenches, and automated verification flows for mixed-signal design.

Language: SystemVerilog - Size: 250 KB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 0 - Forks: 0

chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 855 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 400 - Forks: 76

taichi-ishitani/rice

Language: SystemVerilog - Size: 187 KB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 14 - Forks: 3

fscatox/efes_prj

FPGA + STM32 stepper motor controller with programmable movement pattern, PS/2 keyboard interface, and non-volatile pattern storage. Toy system developed for the "Electronics for Embedded Systems" course at PoliTO

Language: C++ - Size: 27.5 MB - Last synced at: 24 days ago - Pushed at: 25 days ago - Stars: 0 - Forks: 0