GitHub topics: systemverilog

Repositories

SACHINUR17/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: SystemVerilog - Size: 8.76 MB - Last synced at: about 1 hour ago - Pushed at: about 3 hours ago - Stars: 3 - Forks: 0

Awais-Asghar/FPGA-Based-Smart-Car-Security-System

A Smart Anti-Theft Car Security System implemented on FPGA to detect and prevent unauthorized access. The system uses real-time monitoring and control logic to enhance vehicle safety and response.

Language: Verilog - Size: 17.5 MB - Last synced at: about 13 hours ago - Pushed at: about 15 hours ago - Stars: 0 - Forks: 0

Robert-Riordan-UCD/8_Bit_CPU_FPGA

An 8-bit CPU running on a TangNano 9k FPGA. Written in SystemVerilog and tested with PYUVM.

Language: Python - Size: 26.2 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

dalance/svlint

SystemVerilog linter

Language: Rust - Size: 4.23 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 357 - Forks: 42

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 80.3 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 783 - Forks: 44

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 12.6 MB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 342 - Forks: 83

paolopedroso/riscvectorcore

5-Stage RISC-V Processor with Verification Environment

Language: SystemVerilog - Size: 21.7 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

zachjs/sv2v

SystemVerilog to Verilog conversion

Language: Haskell - Size: 2.22 MB - Last synced at: 1 day ago - Pushed at: 3 months ago - Stars: 664 - Forks: 60

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.33 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 32 - Forks: 6

BrianLiDesign/flip-that-digit

A simple game to flip the switch corresponding to the number displayed.

Language: SystemVerilog - Size: 655 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

isaacherink00-svg/fpga-pacman

FPGA implementation of Pac-Man using SystemVerilog and C, developed in Vivado and Vitis.

Language: C - Size: 300 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

F1-uxy/riscv

64-bit RISC-V core (Single cycle and pipelined versions)

Language: SystemVerilog - Size: 38.4 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

topologicalhurt/Thesis

Fpga thesis project. An intelligent hardware scheduling algorithm focused on common signal chains.

Language: Python - Size: 130 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 1

pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language: SystemVerilog - Size: 9.86 MB - Last synced at: 3 days ago - Pushed at: 4 days ago - Stars: 1,366 - Forks: 310

snevindsouza/Numerically_Controlled_Oscillator

The design and implementation of NCO play a critical role in various fields, including communication systems, signal processing, and instrumentation. A versatile NCO using FPGAs is developed, capable of generating a diverse range of waveforms such as sine, cosine, triangular, and square waves.

Language: Shell - Size: 4.45 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

hankhsu1996/slangd

SystemVerilog language server based on Slang frontend

Language: C++ - Size: 423 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 0

Kingfish404/ysyx-workbench

OoO 6-stage CPU (rv32imac_zicntr_zicsr_zifencei).

Language: C - Size: 6.03 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 4 - Forks: 1

Abimael10/anomaly-grid

Sequential pattern analysis through variable-order Markov chains. Built for detecting deviations in finite-alphabet sequences.

Language: Rust - Size: 261 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 7 - Forks: 0

dalance/svls

SystemVerilog language server

Language: Rust - Size: 918 KB - Last synced at: 3 days ago - Pushed at: 8 days ago - Stars: 528 - Forks: 31

calint/tang-nano-20k--riscv--cache-sdram

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card

Language: SystemVerilog - Size: 10.7 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 20 - Forks: 0

calint/tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

Language: SystemVerilog - Size: 6.1 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 39 - Forks: 2

BlueTheDuck/riscv-sv

RV32I implementation written in SystemVerilog

Language: SystemVerilog - Size: 266 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0

kaushalmodi/custom_uvm_report_server

Customized UVM Report Server

Language: SystemVerilog - Size: 424 KB - Last synced at: 1 day ago - Pushed at: over 5 years ago - Stars: 41 - Forks: 10

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 19.4 MB - Last synced at: 4 days ago - Pushed at: 5 days ago - Stars: 1,535 - Forks: 163

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 2 - Forks: 0

saadelahii/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1.01 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 1

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 1

cyril0124/verilua

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Language: Lua - Size: 4.53 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 5 - Forks: 0

SuggarGrandma420/Router-1x3

🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.

Language: JavaScript - Size: 16.4 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

rggen/rggen

Code generation tool for control and status registers

Language: Ruby - Size: 585 KB - Last synced at: 5 days ago - Pushed at: 26 days ago - Stars: 421 - Forks: 55

gopro-uvm-rtl-verification/AXI4-Interconnect-Fabric-Verification-with-UVM

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

Language: SystemVerilog - Size: 44.9 KB - Last synced at: 4 days ago - Pushed at: 23 days ago - Stars: 1 - Forks: 0

rggen/rggen-sv-rtl

Common SystemVerilog RTL modules for RgGen

Language: SystemVerilog - Size: 120 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 13 - Forks: 3

JacobPease/emacsprime

Custom Emacs config with Deus Ex Human Revolution theme.

Language: Emacs Lisp - Size: 688 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

chili-chips-ba/openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

Language: SystemVerilog - Size: 276 MB - Last synced at: 6 days ago - Pushed at: 2 months ago - Stars: 60 - Forks: 15

MPSU/APS

Методические материалы по разработке процессора архитектуры RISC-V

Language: SystemVerilog - Size: 117 MB - Last synced at: 8 days ago - Pushed at: 19 days ago - Stars: 257 - Forks: 65

chaseruskin/orbit

Package manager and build system for VHDL, Verilog, and SystemVerilog

Language: Rust - Size: 62.5 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 56 - Forks: 2

SUHANI102003/50-days-of-Verification

This repo contains the verification basics of System verilog and UVM

Language: SystemVerilog - Size: 3.01 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 1 - Forks: 0

Hithaishisr/Router-1x3

A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

Language: JavaScript - Size: 15.5 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

Slamy/fpga-composite-video

Verilog implementation of PAL, NTSC and SECAM color encoding

Language: Verilog - Size: 664 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 50 - Forks: 8

intel/rohd-hcl

A hardware component library developed with ROHD.

Language: Dart - Size: 40.8 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 102 - Forks: 33

cristian-mattarei/CoSA

CoreIR Symbolic Analyzer

Language: Python - Size: 7.98 MB - Last synced at: 4 days ago - Pushed at: almost 5 years ago - Stars: 74 - Forks: 18

WangXuan95/FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Language: Verilog - Size: 75.2 KB - Last synced at: 5 days ago - Pushed at: almost 2 years ago - Stars: 204 - Forks: 35

MikePopoloski/slang

SystemVerilog compiler and language services

Language: C++ - Size: 31.9 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 823 - Forks: 168

amitops2103/verilog-space-commander

An intelligent, Verilog-based AI fleet controller for the Makerchip ASIC Design Showdown 2025. stellar-strike-ai combines predictive targeting, adaptive defense, and boundary-safe maneuvering to dominate in real-time space combat. Designed using TL-Verilog and fully compatible with the Makerchip simulation environment.

Language: TL-Verilog - Size: 4.99 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 2 - Forks: 0

Karan-nevage/AXI-UVC

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

Language: SystemVerilog - Size: 673 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language: Verilog - Size: 42.6 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 279 - Forks: 75

chili-chips-ba/openCologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Language: Verilog - Size: 296 MB - Last synced at: 6 days ago - Pushed at: 14 days ago - Stars: 68 - Forks: 7

xver/svdb_gateway

SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.

Language: SystemVerilog - Size: 811 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 3 - Forks: 1

jasonrodrig/ALU_SV

Language: SystemVerilog - Size: 1.71 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

heyfey/sv-pathfinder

VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

Language: TypeScript - Size: 7.38 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 3 - Forks: 0

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced at: 10 days ago - Pushed at: over 1 year ago - Stars: 1,198 - Forks: 129

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.28 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 335 - Forks: 82

pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Language: Python - Size: 5.39 MB - Last synced at: 13 days ago - Pushed at: 19 days ago - Stars: 426 - Forks: 56

sifferman/labs-with-cva6

Advanced Architecture Labs with CVA6

Language: SystemVerilog - Size: 311 KB - Last synced at: 11 days ago - Pushed at: over 1 year ago - Stars: 67 - Forks: 27

chili-chips-ba/openPCIE

Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the Host side! Our project roots for Root Complex in 4 ways: 1) openRTL; 2) openBFM with unique sim setup, better performing than vendor TB; 3) openSoftware stack; 4) one-of-the kind openBackplane

Language: HTML - Size: 138 MB - Last synced at: 6 days ago - Pushed at: 13 days ago - Stars: 16 - Forks: 2

charkster/i2c_slave_fpga

Systemverilog implementation of an I2C slave with a simple register map. Multi-byte reads and writes supported with address auto-increment.

Language: SystemVerilog - Size: 37.1 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 3 - Forks: 0

xver/icecream_sv

IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.

Language: SystemVerilog - Size: 275 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 3 - Forks: 0

RDSik/axis-modules

Some AXI-Stream modules

Language: SystemVerilog - Size: 588 KB - Last synced at: about 20 hours ago - Pushed at: about 23 hours ago - Stars: 1 - Forks: 1

Abhimanyu-7/RISC-V

A verilog implementation of RISC-V based processor. coming soon

Language: Verilog - Size: 47.9 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 852 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 407 - Forks: 77

oddball/ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Language: Python - Size: 4.78 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 63 - Forks: 21

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.07 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 708 - Forks: 211

Nambers/0dMIPS

[WIP] in-order 5-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator

Language: C++ - Size: 3.16 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 0 - Forks: 0

Tomas542/MTUCI

Some university subjects from Moscow Technical University of Communications and Informatics (MTUCI) / Московского Технического Университета Связи и Информатики (МТУСИ)

Language: Java - Size: 46 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 1 - Forks: 0

pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Language: SystemVerilog - Size: 106 MB - Last synced at: 11 days ago - Pushed at: 24 days ago - Stars: 135 - Forks: 68

chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Language: C++ - Size: 12.8 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 1,617 - Forks: 250

Harry-Chen/fpga-virtual-console

VT220-compatible console on Cyclone IV EP4CE55F23I7

Language: SystemVerilog - Size: 4.21 MB - Last synced at: 6 days ago - Pushed at: about 7 years ago - Stars: 43 - Forks: 9

cong2738/FlagGame

FlagGame : ISP_RTL_Design(HarmanSA_June_TeamPJ)

Language: SystemVerilog - Size: 71.3 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 1 - Forks: 4

Unicamp-Odhin/MFCC_Core

MFCC Core written in SystemVerilog

Language: Verilog - Size: 2.02 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 2 - Forks: 0

iammituraj/pequeno_riscv

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Language: SystemVerilog - Size: 4.29 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 108 - Forks: 9

trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Language: SystemVerilog - Size: 20.4 MB - Last synced at: 6 days ago - Pushed at: about 5 years ago - Stars: 603 - Forks: 102

TerosTechnology/vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Language: VHDL - Size: 147 MB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 635 - Forks: 56

chipsalliance/UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 4.42 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 229 - Forks: 43