pkpkp456/Learn_System_Verilog

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

Language: Jupyter Notebook - Size: 24.3 MB - Last synced at: about 2 hours ago - Pushed at: about 4 hours ago - Stars: 0 - Forks: 0

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 12.9 MB - Last synced at: about 14 hours ago - Pushed at: about 16 hours ago - Stars: 346 - Forks: 84

antoinemadec/multisim

🏁🧱 speed & interoperability: RTL simulation multi-threading library

Language: SystemVerilog - Size: 450 KB - Last synced at: about 21 hours ago - Pushed at: about 23 hours ago - Stars: 6 - Forks: 0

MikePopoloski/slang

SystemVerilog compiler and language services

Language: C++ - Size: 31.9 MB - Last synced at: about 23 hours ago - Pushed at: 1 day ago - Stars: 870 - Forks: 177

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: about 23 hours ago - Pushed at: 1 day ago - Stars: 3 - Forks: 0

MPSU/APS

Методические материалы по разработке процессора архитектуры RISC-V

Language: SystemVerilog - Size: 117 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 281 - Forks: 69

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 1

saadelahii/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1.01 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 2 - Forks: 1

SuggarGrandma420/Router-1x3

🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.

Language: JavaScript - Size: 16.4 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

Kingfish404/raptor-chip

OoO 6-stage CPU (rv32imac_zicntr_zicsr_zifencei).

Language: C - Size: 6.04 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 7 - Forks: 1

chili-chips-ba/openPCIE

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensource on the Host side too! Our project roots for Root Port in 4 ways: 1) openRTL; 2) openBFM with unique SIM setup, way faster than vendor's; 3) openSW stack; 4) one-of-a-kind openBackplane.

Language: HTML - Size: 172 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 36 - Forks: 3

splinedrive/kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b

Language: Verilog - Size: 200 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 982 - Forks: 68

JesusGMR96/SystemVerilog-Neural-Networks

SystemVerilog implementations of fundamental neural network structures, designed for synthesis on FPGAs.

Language: SystemVerilog - Size: 120 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1 - Forks: 0

dalance/svls

SystemVerilog language server

Language: Rust - Size: 868 KB - Last synced at: 2 days ago - Pushed at: 20 days ago - Stars: 543 - Forks: 31

Nic30/hdlConvertorAst

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Language: Python - Size: 796 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 41 - Forks: 11

oddball/ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Language: VHDL - Size: 5.43 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 63 - Forks: 21

Intuity/forastero

Making cocotb testbenches that bit easier

Language: Python - Size: 196 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 36 - Forks: 3

cyril0124/verilua

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Language: Lua - Size: 4.64 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 6 - Forks: 0

RDSik/sv-modules

Some SV modules

Language: SystemVerilog - Size: 990 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 1 - Forks: 1

dohuyminhdung/PQC_Dilithium

Language: SystemVerilog - Size: 98.6 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 3 - Forks: 0

iammituraj/debouncer

Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

Language: SystemVerilog - Size: 32.2 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 6 - Forks: 2

DatNguyen97-VN/cellrv32

:electron: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.

Language: SystemVerilog - Size: 9.35 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 5 - Forks: 1

hankhsu1996/slangd

SystemVerilog language server based on Slang frontend

Language: C++ - Size: 926 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 0

SystemRDL/PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Language: Python - Size: 930 KB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 71 - Forks: 56

olofk/edalize

An abstraction library for interfacing EDA tools

Language: Python - Size: 1.08 MB - Last synced at: 2 days ago - Pushed at: 15 days ago - Stars: 718 - Forks: 218

Ryoga-exe/cojt-hw

University of Tsukuba COJT Embedded Systems OJT Hardware Course assignments

Language: Verilog - Size: 6.56 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

hudson-trading/slang-server

A SystemVerilog language server based on the Slang library.

Language: C++ - Size: 16.8 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 52 - Forks: 4

Unicamp-Odhin/MFCC_Core

MFCC Core written in SystemVerilog

Language: Verilog - Size: 37.4 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 2 - Forks: 0

kimpro82/MyPractice

Born in October and learn like octopus

Language: Python - Size: 21 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

dalance/sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

Language: Rust - Size: 48.2 MB - Last synced at: 1 day ago - Pushed at: 8 months ago - Stars: 452 - Forks: 61

Lamagraph/intro-to-fpga-with-clash

Materials to start FPGA programming with SystemVerilog and Clash

Language: SystemVerilog - Size: 2.27 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 2 - Forks: 2

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 20.1 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1,549 - Forks: 164

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 81 MB - Last synced at: 7 days ago - Pushed at: 9 days ago - Stars: 809 - Forks: 47

KastnerRG/cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Language: SystemVerilog - Size: 20 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 95 - Forks: 15

Choaib-ELMADI/getting-started-with-systemverilog

Getting started with SystemVerilog: Hardware Description Language for design and verification.

Language: SystemVerilog - Size: 1.02 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 6 - Forks: 1

ericpearson1313/fdtd2d-verilog

WIP: a FPGA implementation of a 2D simulation of EM wave propagation using an FDTD (finite difference time domain) method. Purpose is to understand the FPGA benefits and limits on performance of the FDTD iterative cellular array based calculation.

Language: SystemVerilog - Size: 82 KB - Last synced at: 10 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

TatsuProject/chipforge_eda_server

EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

Language: Python - Size: 32.3 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Language: Python - Size: 19.5 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 218 - Forks: 29

tsfpga/tsfpga

A flexible and scalable development platform for modern FPGA projects.

Language: Python - Size: 2.36 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 36 - Forks: 7

alirazajiwani/UART

UART is a serial communication protocol used to transmit and receive data one bit at a time without a clock signal.

Language: SystemVerilog - Size: 5.52 MB - Last synced at: 11 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

mshr-h/vscode-verilog-hdl-support

HDL support for VS Code

Language: TypeScript - Size: 2.28 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 340 - Forks: 83

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language: Verilog - Size: 43 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 291 - Forks: 80

TerosTechnology/vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Language: VHDL - Size: 152 MB - Last synced at: 10 days ago - Pushed at: about 1 month ago - Stars: 654 - Forks: 57

topologicalhurt/Thesis

Fpga thesis project. An intelligent hardware scheduling algorithm focused on common signal chains.

Language: Python - Size: 136 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 2 - Forks: 1

pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language: SystemVerilog - Size: 9.89 MB - Last synced at: 13 days ago - Pushed at: 14 days ago - Stars: 1,386 - Forks: 314

rggen/rggen

Code generation tool for control and status registers

Language: Ruby - Size: 594 KB - Last synced at: 9 days ago - Pushed at: about 2 months ago - Stars: 427 - Forks: 55

openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Language: Assembly - Size: 112 MB - Last synced at: 13 days ago - Pushed at: 14 days ago - Stars: 602 - Forks: 259

aliadelmahdi/SystemVerilog-Scheduling-Semantics-Examples

This repository contains example SystemVerilog source files from the paper “SystemVerilog Scheduling Semantics”.

Size: 9.77 KB - Last synced at: 13 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

ppalazon/hspecid-x

HSpecID-X: A Hyperspectral Pixel Classifier Accelerator for X-HEEP

Language: SystemVerilog - Size: 1.23 MB - Last synced at: 14 days ago - Pushed at: 15 days ago - Stars: 0 - Forks: 1

chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language: C++ - Size: 855 MB - Last synced at: 10 days ago - Pushed at: about 2 months ago - Stars: 422 - Forks: 77

ShankhalikaMallick/System_Verilog

some more practice in system verilog

Language: SystemVerilog - Size: 9.77 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 0 - Forks: 0

BIG-Denis/karavaisv

Powerful yet simple-to-use templating engine for SystemVerilog with plenty of useful features.

Size: 12.7 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 1 - Forks: 0

pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Language: Python - Size: 5.39 MB - Last synced at: 2 days ago - Pushed at: 2 months ago - Stars: 431 - Forks: 57

zachjs/sv2v

SystemVerilog to Verilog conversion

Language: Haskell - Size: 2.22 MB - Last synced at: 18 days ago - Pushed at: 4 months ago - Stars: 670 - Forks: 60

fuad1502/oombak

Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!

Language: Rust - Size: 22.6 MB - Last synced at: 5 days ago - Pushed at: 20 days ago - Stars: 43 - Forks: 2

dalance/svlint

SystemVerilog linter

Language: Rust - Size: 4.23 MB - Last synced at: 10 days ago - Pushed at: about 2 months ago - Stars: 360 - Forks: 42

WangXuan95/FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Language: Verilog - Size: 75.2 KB - Last synced at: 7 days ago - Pushed at: about 2 years ago - Stars: 211 - Forks: 36

periareon/rules_verilog

Bazel rules for Verilog synthesis

Language: Starlark - Size: 1.09 MB - Last synced at: 12 days ago - Pushed at: 22 days ago - Stars: 0 - Forks: 0

Ka10kenHQ/FloatingPointUnit

IEEE-754 Compliant Floating Point Unit (FPU)

Language: SystemVerilog - Size: 2.01 MB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 3 - Forks: 0

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced at: 16 days ago - Pushed at: over 1 year ago - Stars: 1,201 - Forks: 130

vyges/uart-controller

A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.

Language: SystemVerilog - Size: 306 KB - Last synced at: 22 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

vyges/full-adder-ip

A configurable full adder IP with three implementation approaches (simple XOR/AND, modular half adder, carry lookahead) following Vyges conventions. Includes comprehensive verification with SystemVerilog, UVM, and Cocotb testbenches supporting multiple simulators (Icarus, Verilator, Questa, VCS, Xcelium). Production-ready for ASIC/FPGA w/ 500MHz

Language: Python - Size: 325 KB - Last synced at: 22 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

vyges/vyges-ip-template

🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

Language: Python - Size: 389 KB - Last synced at: 22 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

vyges/vybox-lite

VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.

Language: JavaScript - Size: 37.1 KB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

Ismailo667/aes-rtl-validation

AES-128 co-simulation between SystemVerilog, C DPI, and Python for hardware verification.

Language: Verilog - Size: 38.1 KB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Language: SystemVerilog - Size: 106 MB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 141 - Forks: 73

chaseruskin/orbit

Package manager and build system for VHDL, Verilog, and SystemVerilog

Language: Rust - Size: 62.7 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 57 - Forks: 2

dau-dev/verilator-python

Python/PyPI wrapper for Verilator

Language: Python - Size: 89.8 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 4 - Forks: 0

ErikMeinders/sv2svg

SystemVerilog (.sv) to SVG visualizer using Schemdraw logic gates.

Language: Python - Size: 151 KB - Last synced at: 23 days ago - Pushed at: 25 days ago - Stars: 2 - Forks: 0

daniel-pg/ArchRival-Core

ArchRival is a clean SystemVerilog implementation of the ICMC-Processor, redesigned at UNICAMP 😎

Size: 8.79 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 2 - Forks: 0

marcovins/fpga-verification-scripts

Language: SystemVerilog - Size: 231 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 1 - Forks: 0

midisenpai/rtl-core-library

A set of common RTL cores that I've developed over time and organized into a FuseSoC library.

Size: 43 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 8 - Forks: 1

certainly-param/garuda-accelerator

Garuda: Swift RISC-V INT8 accelerator for neural network inference. CVXIF coprocessor for CVA6 achieving 2-5x speedup.

Language: SystemVerilog - Size: 11.7 KB - Last synced at: 22 days ago - Pushed at: 26 days ago - Stars: 0 - Forks: 0

shehanmunasinghe/tinyGPU

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

Language: SystemVerilog - Size: 1.23 MB - Last synced at: 2 days ago - Pushed at: over 4 years ago - Stars: 51 - Forks: 12

trivialmips/nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

Language: SystemVerilog - Size: 20.4 MB - Last synced at: 4 days ago - Pushed at: over 5 years ago - Stars: 601 - Forks: 102

intel/rohd-hcl

A hardware component library developed with ROHD.

Language: Dart - Size: 37.8 MB - Last synced at: 7 days ago - Pushed at: 23 days ago - Stars: 104 - Forks: 33

martinKindall/risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

Language: SystemVerilog - Size: 40 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 51 - Forks: 3

suzizecat/slang-lsp-tools

Tools based upon slang for language server purpose

Language: C++ - Size: 358 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 17 - Forks: 2

dominiksalvet/super-riscv

Superscalar dual-issue RISC-V processor

Language: SystemVerilog - Size: 1.82 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 9 - Forks: 3

chili-chips-ba/openCologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

Language: Verilog - Size: 296 MB - Last synced at: 26 days ago - Pushed at: 2 months ago - Stars: 73 - Forks: 7

openhwgroup/core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Language: SystemVerilog - Size: 36.6 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 187 - Forks: 65

t-f-marfil/VerilogWriter.jl

A package to generate Verilog/SystemVerilog code on Julia.

Language: Julia - Size: 2.06 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 3 - Forks: 0

iammituraj/pequeno_riscv

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Language: SystemVerilog - Size: 5.09 MB - Last synced at: 30 days ago - Pushed at: 30 days ago - Stars: 115 - Forks: 10

wyvernSemi/vproc

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

Language: VHDL - Size: 14.1 MB - Last synced at: 27 days ago - Pushed at: about 1 month ago - Stars: 65 - Forks: 12

Ali-975/DV_Training_NCDC

Design Verification (DV) Engineer Training at NCDC, Islamabad — covering C programming, Assembly, RISC-V ISA, SystemVerilog, Computer Architecture, UVM Methodology, and other verification concepts.

Language: Tcl - Size: 201 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

rggen/rggen-sample-testbench

Language: VHDL - Size: 617 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 14 - Forks: 5

chili-chips-ba/openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

Language: SystemVerilog - Size: 276 MB - Last synced at: 25 days ago - Pushed at: 4 months ago - Stars: 64 - Forks: 15

DMoore12/sv-sim

A simple SystemVerilog simulation tool written in rust

Language: Rust - Size: 854 KB - Last synced at: 11 days ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

SystemRDL/PeakRDL

Control and status register code generator toolchain

Language: Python - Size: 154 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 145 - Forks: 31

opendv360/verification-diagrams

This collection of verification diagrams is created to help educators, students, and engineers visualize complex hardware verification concepts. These illustrations transform complex concepts into understandable visuals.

Size: 35.5 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 2 - Forks: 0

shinolab/autd3-old-monorepo 📦

Airborne Ultrasound Tactile Display 3

Size: 28.5 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 15 - Forks: 2

Karan-nevage/HDLBits-Complete-Solutions

HDLBits Complete Solutions A repository containing complete solutions for all HDLBits exercises, a platform designed to help learners practice digital hardware design using Verilog. The solutions cover topics ranging from basic Verilog syntax to advanced circuit design challenges, ensuring a smooth learning curve.

Language: Verilog - Size: 49.8 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

hankhsu1996/vscode-better-systemverilog-syntax

Better SystemVerilog Syntax for VS Code

Language: SystemVerilog - Size: 1.69 MB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 8 - Forks: 1

suzizecat/diplomat-vscode

System verilog support VS Code Extension

Language: TypeScript - Size: 436 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 5 - Forks: 1

MohamedHussein27/SPI-with-RAM-SV

SystemVerilog-based verification environment for an SPI Slave with Single-Port RAM. Includes transactions, driver, monitor, scoreboard, assertions, and coverage collection to create a self-checking and coverage-driven testbench.

Language: SystemVerilog - Size: 2.83 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

Intuity/packtype

Packed data structure specifications for multi-language hardware projects.

Language: Python - Size: 387 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 11 - Forks: 2

Robert-Riordan-UCD/8_Bit_CPU_FPGA

An 8-bit CPU running on a TangNano 9k FPGA. Written in SystemVerilog and tested with PYUVM.

Language: Python - Size: 26.4 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

Karan-nevage/AXI-UVC

Reusable AXI Universal Verification Component built with SystemVerilog and UVM. Integrates into any testbench to accelerate design verification with modular agents, monitors, drivers, coverage, and scoreboard.

Language: SystemVerilog - Size: 781 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

sifferman/labs-with-cva6

Advanced Architecture Labs with CVA6

Language: SystemVerilog - Size: 311 KB - Last synced at: 17 days ago - Pushed at: almost 2 years ago - Stars: 68 - Forks: 27

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.7 MB - Last synced at: 10 days ago - Pushed at: 6 months ago - Stars: 44 - Forks: 11