GitHub topics: systemverilog

Repositories

saadelahii/JTAG-IEEE-1149.1

Basic JTAG standard implementation in Verilog and integration with a CUT

Language: Verilog - Size: 1.01 MB - Last synced at: about 5 hours ago - Pushed at: about 6 hours ago - Stars: 2 - Forks: 1

dianluniuniu/async-fifo

Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog

Language: SystemVerilog - Size: 25.4 KB - Last synced at: about 7 hours ago - Pushed at: about 8 hours ago - Stars: 0 - Forks: 0

dianluniuniu/clock-management-unit

A comprehensive clock management IP core with multiple divider types and glitch-free switching

Language: Verilog - Size: 25.4 KB - Last synced at: about 6 hours ago - Pushed at: 18 days ago - Stars: 0 - Forks: 0

MikePopoloski/slang

SystemVerilog compiler and language services

Language: C++ - Size: 32.2 MB - Last synced at: about 10 hours ago - Pushed at: about 10 hours ago - Stars: 882 - Forks: 185

franos-cm/shake-sv

SystemVerilog implementation of SHAKE128/256 cryptographic hash functions

Language: SystemVerilog - Size: 151 KB - Last synced at: about 10 hours ago - Pushed at: about 11 hours ago - Stars: 0 - Forks: 0

MohamedHussein27/SPI-with-RAM-SV

SystemVerilog-based verification environment for an SPI Slave with Single-Port RAM. Includes transactions, driver, monitor, scoreboard, assertions, and coverage collection.

Language: SystemVerilog - Size: 2.83 MB - Last synced at: about 10 hours ago - Pushed at: about 12 hours ago - Stars: 0 - Forks: 0

SuggarGrandma420/Router-1x3

🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.

Language: JavaScript - Size: 16.4 MB - Last synced at: about 16 hours ago - Pushed at: about 17 hours ago - Stars: 0 - Forks: 0

jasonyu1996/anvil

Language: OCaml - Size: 1.09 MB - Last synced at: about 20 hours ago - Pushed at: about 21 hours ago - Stars: 15 - Forks: 2

elshazlio/elevator-controller-fpga

Elevator controller design and FPGA implementation using SystemVerilog

Language: SystemVerilog - Size: 49.8 KB - Last synced at: about 24 hours ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 1

cyril0124/verilua

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Language: Lua - Size: 4.83 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 7 - Forks: 0

msinger/dmg-sim

SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip

Language: SystemVerilog - Size: 753 KB - Last synced at: 1 day ago - Pushed at: 2 days ago - Stars: 6 - Forks: 1

zachjs/sv2v

SystemVerilog to Verilog conversion

Language: Haskell - Size: 1.94 MB - Last synced at: 1 day ago - Pushed at: 19 days ago - Stars: 674 - Forks: 60

shinolab/autd3-firmware

Language: SystemVerilog - Size: 891 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1 - Forks: 0

SazzadSowmik/HiVeGen-Pipeline-Reproduction

Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).

Language: SystemVerilog - Size: 268 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0

MochiButter/risc-v-core

rv64/32i core

Language: SystemVerilog - Size: 111 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Language: Python - Size: 19.2 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 218 - Forks: 29

clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Language: Haskell - Size: 20 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 1,554 - Forks: 164

dshekhalev/FEC

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

Language: SystemVerilog - Size: 1.39 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 124 - Forks: 38

chaseruskin/verb

A verification library for digital hardware

Language: Python - Size: 2.02 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 5 - Forks: 0

chaseruskin/orbit

Package manager and build system for VHDL, Verilog, and SystemVerilog

Language: Rust - Size: 61 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 57 - Forks: 2

jeffreyc-dev/rv32im-5stage-cpu

A 5-stage, in order, pipelined upgrade of the single-cycle RV32I CPU in SystemVerilog. Includes the RISC-V "M" extension (multiply/divide) with multi-cycle arithmetic units and a hazard unit with data forwarding. Dynamic branch prediction to be added soon.

Language: SystemVerilog - Size: 1.79 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

WilliamdeSousa/projeto-de-sistemas-digitais

Language: SystemVerilog - Size: 11.7 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

ablomm/ablomm-cpu

A 32-bit CPU and Assembler

Language: Rust - Size: 449 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 20 - Forks: 0

pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Language: SystemVerilog - Size: 106 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 152 - Forks: 81

SystemRDL/PeakRDL

Control and status register code generator toolchain

Language: Python - Size: 173 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 152 - Forks: 33

RDSik/sv-modules

Some SV modules

Language: SystemVerilog - Size: 1.09 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 1

ppalazon/hspecid-x

HSpecID-X: A Hyperspectral Pixel Classifier Accelerator for X-HEEP

Language: SystemVerilog - Size: 5.16 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 1

daniel-pg/ArchRival-Core

ArchRival is a clean SystemVerilog implementation of the ICMC-Processor, redesigned at UNICAMP 😎

Size: 19.5 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 3 - Forks: 0

splinedrive/kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b

Language: Verilog - Size: 200 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 983 - Forks: 68

hudson-trading/slang-server

A SystemVerilog language server based on the Slang library.

Language: C++ - Size: 16.9 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 62 - Forks: 8

jeras/TCB

Tightly Coupled Bus, low complexity, high performance system bus.

Language: SystemVerilog - Size: 1.08 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 6 - Forks: 0

BegangLive/VLSI-Design-Verification-Projects

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

Language: Stata - Size: 20.5 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 3 - Forks: 0

mattyoung101/slingshot

SystemVerilog LSP. Strives to be fast and accurate with a special focus on autocomplete.

Language: C++ - Size: 1.33 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 3 - Forks: 0

SystemRDL/PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Language: Python - Size: 959 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 71 - Forks: 54

Nambers/0dMIPS

[WIP] in-order 5-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator

Language: C++ - Size: 3.23 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 6 - Forks: 1

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 13 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 347 - Forks: 84

chili-chips-ba/openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

Language: SystemVerilog - Size: 276 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 70 - Forks: 15

capopaul/Public-Verilog-Design-Flow-And-Environment

Provide a basic structure to starts a Verilog or Systemverilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)

Language: Python - Size: 27.3 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

Yashas2801/apb_gpio_verification

This repository contains a comprehensive UVM-based verification environment in SystemVerilog for a 32-bit APB GPIO controller.

Language: SystemVerilog - Size: 34.7 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 1

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 81.3 MB - Last synced at: 6 days ago - Pushed at: 7 days ago - Stars: 827 - Forks: 49

chili-chips-ba/openPCIE

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensource on the Host side too! Our project roots for Root Port in 4 ways: 1) openRTL; 2) openBFM with unique SIM setup, way faster than vendor's; 3) openSW stack; 4) one-of-a-kind openBackplane.

Language: HTML - Size: 182 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 39 - Forks: 3

MPSU/APS

Методические материалы по разработке процессора архитектуры RISC-V

Language: SystemVerilog - Size: 116 MB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 283 - Forks: 70

lockedloop/asd

Simple personal tooling for quickly bootstrapping hardware development projects using open-source tools (Verilator, cocotb, TOML-based configuration)

Language: Python - Size: 198 KB - Last synced at: 10 days ago - Pushed at: 10 days ago - Stars: 0 - Forks: 0

marcovins/fpga-verification-scripts

Language: SystemVerilog - Size: 257 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 1 - Forks: 0

dau-dev/verilator-python

Python/PyPI wrapper for Verilator

Language: Python - Size: 107 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 4 - Forks: 0

siliscale/Tiny-Vedas

A highly-configurable RISC-V Core

Language: SystemVerilog - Size: 5.34 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 25 - Forks: 4

hankhsu1996/slangd

SystemVerilog language server based on Slang frontend

Language: C++ - Size: 1.15 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 2 - Forks: 0

ckvespinoza/Cyber-War-Linear-Feedback-Shift-Register

Continuation of Tug of War but instead replaces player 2 with a randomizer (created by taking the 7th and 10th taps of a 10-bit LFSR to XNOR into an input and using a comparator with the resulting 10-bit register with manually selected SW[8:0])

Language: SystemVerilog - Size: 34.2 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

ckvespinoza/Tug-of-War

2-player game using DE1-SoC board for tug of war using LED and KEY. #SystemVerilog

Language: SystemVerilog - Size: 30.3 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

ckvespinoza/Control-Station-Flight-Line-Hazard-Lights

Basic design for hazard lights that communicate the direction of wind through different patterns to landing pilots. #SystemVerilog

Language: SystemVerilog - Size: 27.3 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

ckvespinoza/Shop-Lifting-System

#SystemVerilog

Language: Tcl - Size: 18.6 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

ckvespinoza/Intro-to-Seven-Segment-Display

#SystemVerilog

Language: Tcl - Size: 17.6 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

ckvespinoza/Quartus-and-Model-Sim-Tutorial

Refer to for refresher on Quartus and ModelSim. #SystemVerilog

Language: Tcl - Size: 4.73 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

ckvespinoza/Multi-Digit-Recognizer

Write a Verilog program that compares two 2-digit numbers (for example, the last two digits of your student ID and your partner’s). If both digits match, light up LEDR[0]. #SystemVerilog

Language: Tcl - Size: 16.6 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 0 - Forks: 0

RadioPizza/TPU-Labs-FPGA-basics

This repository serves as a collection of laboratory assignments completed during the "Basics of FPGA" course

Language: SystemVerilog - Size: 17.4 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 0

pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language: Verilog - Size: 43 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 296 - Forks: 83

rggen/rggen-systemverilog

SystemVerilog RTL and UVM RAL model generators for RgGen

Language: Ruby - Size: 729 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 14 - Forks: 2

Team-gonghack/gonghack-PL

FPGA PL 부분, I2C FSM로직 구현 및 AXI-Lite와 AXI-Stream을 이용해서 DMA구현, AI연산을 DPU로 구현해 AI를 하드웨어로 가속

Language: VHDL - Size: 163 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 1

heyfey/sv-pathfinder

VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

Language: TypeScript - Size: 16.4 MB - Last synced at: 14 days ago - Pushed at: 15 days ago - Stars: 29 - Forks: 0

TatsuProject/chipforge_eda_server

EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

Language: Python - Size: 32.3 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 1 - Forks: 0

Nic30/hdlConvertorAst

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

Language: Python - Size: 801 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 41 - Forks: 11

ridoluc/rvcpu-rv32im-soc

A compact SystemVerilog SoC implementing a RV32IM CPU with memory‑mapped GPIO, UART and Timer peripherals on a Wishbone bus. Instruction memory is JTAG‑programmable and the repo includes Verilator testbenches plus a gcc-based toolchain to build C programs and generate Verilog‑readable instruction images.

Language: SystemVerilog - Size: 287 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 1 - Forks: 0

Choaib-ELMADI/getting-started-with-systemverilog

Getting started with SystemVerilog: Hardware Description Language for design and verification.

Language: SystemVerilog - Size: 1.26 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 7 - Forks: 1

Kingfish404/raptor-chip

OoO 6-stage CPU (rv32imac_zicntr_zicsr_zifencei).

Language: C - Size: 6.09 MB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 7 - Forks: 1

noumidev/mina2000-electrocute

Pipelined MINAv2 softcore written in SystemVerilog. Designed for Sipeed Tang Primer 20K. Work in progress.

Language: SystemVerilog - Size: 37.1 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 0 - Forks: 0

dominiksalvet/super-riscv

Superscalar dual-issue RISC-V processor

Language: SystemVerilog - Size: 1.85 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 10 - Forks: 4

WangXuan95/FPGA-FixedPoint

Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Language: Verilog - Size: 75.2 KB - Last synced at: 15 days ago - Pushed at: about 2 years ago - Stars: 213 - Forks: 36

dalance/svlint

SystemVerilog linter

Language: Rust - Size: 4.35 MB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 365 - Forks: 43

hdl-util/hdmi

Send video/audio over HDMI on an FPGA

Language: SystemVerilog - Size: 4.13 MB - Last synced at: 16 days ago - Pushed at: almost 2 years ago - Stars: 1,208 - Forks: 131

iammituraj/skid_buffer

Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

Language: SystemVerilog - Size: 47.9 KB - Last synced at: 17 days ago - Pushed at: 18 days ago - Stars: 26 - Forks: 8

AUDIY/Questa_Verification_Tutorials

Examples for the Questa本 (Tentative)

Language: Verilog - Size: 43 KB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 0 - Forks: 0

loykylewong/FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Language: Scala - Size: 3.21 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 132 - Forks: 31

iammituraj/fifo

Synchronous FIFOs designed in Verilog/System Verilog.

Language: SystemVerilog - Size: 78.1 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 19 - Forks: 8

intel/rohd-hcl

A hardware component library developed with ROHD.

Language: Dart - Size: 39.2 MB - Last synced at: 20 days ago - Pushed at: 28 days ago - Stars: 104 - Forks: 33

pkpkp456/Learn_System_Verilog

Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.

Language: Jupyter Notebook - Size: 24.3 MB - Last synced at: 21 days ago - Pushed at: 22 days ago - Stars: 0 - Forks: 0

antoinemadec/multisim

🏁🧱 speed & interoperability: RTL simulation multi-threading library

Language: SystemVerilog - Size: 450 KB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 6 - Forks: 0

Intuity/packtype

Packed data structure specifications for multi-language hardware projects.

Language: Python - Size: 338 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 13 - Forks: 2

JesusGMR96/SystemVerilog-Neural-Networks

SystemVerilog implementations of fundamental neural network structures, designed for synthesis on FPGAs.

Language: SystemVerilog - Size: 120 KB - Last synced at: 24 days ago - Pushed at: 24 days ago - Stars: 1 - Forks: 0

mikeroyal/Verilog-SystemVerilog-Guide

Verilog/SystemVerilog Guide

Language: SystemVerilog - Size: 19.5 KB - Last synced at: 18 days ago - Pushed at: almost 2 years ago - Stars: 74 - Forks: 11

clin99/awesome-eda

Size: 51.8 KB - Last synced at: 15 days ago - Pushed at: over 6 years ago - Stars: 94 - Forks: 17

dalance/svls

SystemVerilog language server

Language: Rust - Size: 868 KB - Last synced at: 23 days ago - Pushed at: about 1 month ago - Stars: 543 - Forks: 31

oddball/ipxact2systemverilog

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

Language: VHDL - Size: 5.43 MB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 63 - Forks: 21

Intuity/forastero

Making cocotb testbenches that bit easier

Language: Python - Size: 196 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 36 - Forks: 3

dohuyminhdung/PQC_Dilithium

Language: SystemVerilog - Size: 98.6 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 3 - Forks: 0

iammituraj/debouncer

Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

Language: SystemVerilog - Size: 32.2 KB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 6 - Forks: 2

DatNguyen97-VN/cellrv32

:electron: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.

Language: SystemVerilog - Size: 9.35 MB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 5 - Forks: 1