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GitHub / BrianHGinc / BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BrianHGinc%2FBrianHG-DDR3-Controller
Stars: 64
Forks: 28
Open Issues: 0
License: None
Language: SystemVerilog
Repo Size: 9.94 MB
Dependencies:
0
Created: almost 3 years ago
Updated: about 2 months ago
Last pushed: about 2 months ago
Last synced: about 2 months ago
Topics: altera, ddr3, fpga, hdl, intel, lattice, systemverilog, testbenches, verilog, xilinx
Files
No dependencies found