Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: testbenches
BrianHGinc/BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Language: SystemVerilog - Size: 9.94 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 64 - Forks: 28
geddy11/netwiz
Network protocol libraries for VHDL test benches
Language: VHDL - Size: 655 KB - Last synced: 2 months ago - Pushed: 7 months ago - Stars: 5 - Forks: 0
VLSI-EDA/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Language: VHDL - Size: 4.96 MB - Last synced: about 2 months ago - Pushed: over 3 years ago - Stars: 511 - Forks: 95
tmeissner/libvhdl
Library of reusable VHDL components
Language: VHDL - Size: 263 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 24 - Forks: 3
Shehab-Naga/VHDL-Exercises
My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.
Language: VHDL - Size: 1.44 MB - Last synced: 5 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0
Saadia-Hassan/Types-of-Verification-Using-SRAM
This repo contains golden vector and randomization testbenches for SRAM module.
Language: Verilog - Size: 7.81 KB - Last synced: 7 months ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 2
TILhub/AMBA-3-AHB-Lite-Protocol
This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
Language: C++ - Size: 327 KB - Last synced: 7 months ago - Pushed: almost 6 years ago - Stars: 10 - Forks: 3
nxbyte/Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
Language: Verilog - Size: 2.23 MB - Last synced: 7 months ago - Pushed: over 4 years ago - Stars: 91 - Forks: 21
leonardogargani/working_zone_encoding
Implementation of a low-power enconding technique.
Language: VHDL - Size: 854 KB - Last synced: 10 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0
AlPrime2k1/Sequential-Logic-Circuits
Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits
Language: Verilog - Size: 22.5 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0
Crimsonninja/senior_design_puf
Repository to store all design and testbench files for Senior Design
Language: Verilog - Size: 1.57 MB - Last synced: 9 months ago - Pushed: about 4 years ago - Stars: 13 - Forks: 6
mihir8181/VerilogHDL-Codes
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
Language: Verilog - Size: 3.45 MB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 21 - Forks: 3
tmeissner/cryptocores
cryptography ip-cores in vhdl / verilog
Language: VHDL - Size: 238 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 37 - Forks: 9
kuby1412/Open-Source-Verilog-Projects
This repository contains source code for labs and projects involving FPGA and Verilog based designs
Language: Verilog - Size: 133 KB - Last synced: about 1 year ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0
Mahmoud-geberty/Hardware_Design_Projects
A repository where I intend to upload most Hardware design projects I make.
Language: SystemVerilog - Size: 25.4 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 0 - Forks: 0
ste7en/Project-Reti-Logiche-Testbench-Generator
A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.
Language: C - Size: 15.6 KB - Last synced: about 1 year ago - Pushed: over 5 years ago - Stars: 2 - Forks: 0