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GitHub / ste7en / Project-Reti-Logiche-Testbench-Generator

A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ste7en%2FProject-Reti-Logiche-Testbench-Generator

Stars: 2
Forks: 0
Open issues: 0

License: gpl-3.0
Language: C
Size: 15.6 KB
Dependencies parsed at: Pending

Created at: over 6 years ago
Updated at: about 4 years ago
Pushed at: over 6 years ago
Last synced at: about 2 years ago

Topics: c, testbench, testbenches, vhdl

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