GitHub topics: hdl

Repositories

younessili/HGG

Hardware Graph Generator HGG

Language: Python - Size: 41 KB - Last synced at: about 1 hour ago - Pushed at: about 3 hours ago - Stars: 4 - Forks: 1

paolopedroso/riscvectorcore

5-Stage RISC-V Processor with Verification Environment

Language: SystemVerilog - Size: 21.8 MB - Last synced at: about 6 hours ago - Pushed at: about 7 hours ago - Stars: 1 - Forks: 0

langhuihui/monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

Language: Go - Size: 43.8 MB - Last synced at: about 7 hours ago - Pushed at: about 8 hours ago - Stars: 1,995 - Forks: 288

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 12.2 MB - Last synced at: about 23 hours ago - Pushed at: 1 day ago - Stars: 327 - Forks: 82

pc2/sus-compiler

A new Hardware Design Language that keeps you in the driver's seat

Language: Rust - Size: 18.1 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 83 - Forks: 5

VHDL/PoC Fork of VLSI-EDA/PoC

IP Core Library - Published and maintained by the Open Source VHDL Group

Language: VHDL - Size: 10.8 MB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 13 - Forks: 1

Wayrix70/pytcl

Read-only mirror of https://gitlab.com/tymonx/pytcl

Language: Python - Size: 26.4 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 1

Intuity/forastero

Making cocotb testbenches that bit easier

Language: Python - Size: 252 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 29 - Forks: 1

richnou/kissb

KISSB - A Flexible Multi-Language build system

Language: Tcl - Size: 579 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 0 - Forks: 0

analogdevicesinc/hdl

HDL libraries and projects

Language: Verilog - Size: 87.4 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 1,665 - Forks: 1,569

NellyW8/VeriReason

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Language: Python - Size: 256 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 3 - Forks: 1

XedaHQ/xeda

Cross EDA Abstraction and Automation

Language: Python - Size: 128 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 39 - Forks: 5

yomnahisham/ts-verilog-simulator

A web-based Verilog simulator for designing, running, and visualizing RTL code in-browser. Built with Next.js 14, TypeScript, Tailwind CSS, and Monaco Editor on the frontend, and FastAPI with a custom Python simulation engine on the backend with real-time simulation, interactive waveform viewing, multi-file support, and automated module detection.

Language: TypeScript - Size: 300 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 5 - Forks: 0

vishnu-patil01/vishnu-patil01

Beginner-level Verilog HDL programs for practicing fundamental digital design concepts like logic gates and multiplexers. Perfect for students learning VLSI and HDL design.

Size: 4.88 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

vishnu-patil01/verilog-practice

Beginner-level Verilog HDL programs for digital design and simulation practice.

Language: Verilog - Size: 1.95 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

Choaib-ELMADI/risc-v-on-de2-soc-fpga

A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.

Language: Verilog - Size: 24.4 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 5 - Forks: 2

Elihelmo/Kintex-7-MIPI-DSI-6.9-inch-LCD

This repository contains a Verilog-based HDL design for driving a 6.9-inch MIPI DSI LCD using the Kintex-7 FPGA. Explore the project to simplify your display initialization without relying on complex IPs. 🖥️🌟

Size: 2.14 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

aappleby/metron

A C++ to Verilog translation tool with some basic guarantees that your code will work.

Language: C++ - Size: 86.1 MB - Last synced at: 3 days ago - Pushed at: 4 months ago - Stars: 170 - Forks: 14

priyanshscpp/E3042-VLSI-Design

RISC_V x32 enhanced for AI/ML Neural Networking and Signal Processing

Language: Verilog - Size: 66.4 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

stnolting/neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Language: VHDL - Size: 226 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1,780 - Forks: 265

K4V4NH/Basic-Verilog-Codes

Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.

Language: Verilog - Size: 18.6 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Language: Rust - Size: 78.6 MB - Last synced at: 5 days ago - Pushed at: 6 days ago - Stars: 707 - Forks: 37

asyncvlsi/act

ACT hardware description language and core tools.

Language: C++ - Size: 4.94 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 110 - Forks: 27

chaseruskin/orbit

Package manager and build system for VHDL, Verilog, and SystemVerilog

Language: Rust - Size: 59.6 MB - Last synced at: 3 days ago - Pushed at: 13 days ago - Stars: 47 - Forks: 2

shrine-maiden-heavy-industries/torii-boards

Torii HDL Board Definitions

Language: Python - Size: 58.6 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 0 - Forks: 0

DFiantHDL/DFHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

Language: Scala - Size: 50.5 MB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 85 - Forks: 11

Vishwajeetsinh-K/RTL2GDS_demux

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.

Size: 4.88 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

eliainnocenti/HES-Laboratories

Laboratories for Hardware and Embedded Security Exam @ Polito - Materials and supporting documentation for the HES Labs.

Language: Verilog - Size: 158 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

kagandikmen/V-FRONT

Where it all begins: FIve-stage 32-bit RISC-V CPU in Verilog (Educational, RV32I 2.1 compliant, Zicsr, Zifencei)

Language: C - Size: 1.28 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 0 - Forks: 0

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

Language: Python - Size: 18.9 MB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 12 - Forks: 4

Munees-Sanid/verilog_code_challenge

Verilog Code Challenge – KVLSI Kohort 2

Language: Verilog - Size: 1.32 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 3 - Forks: 0

briansune/FPGA-TFT-MIPI-or-DPI

FPGA-TFT-MIPI-or-DPI

Size: 9.28 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 1 - Forks: 0

briansune/FPGA-LCD-MIPI-or-DPI

FPGA LCD MIPI or DPI

Size: 14.5 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 2 - Forks: 0

ktbarrett/coconext

Staging area for new features of cocotb

Language: Python - Size: 30.3 KB - Last synced at: 7 days ago - Pushed at: 10 days ago - Stars: 1 - Forks: 0

nananapo/veryl-riscv-book

Let's write RISC-V CPU in Veryl!

Language: HTML - Size: 139 MB - Last synced at: 9 days ago - Pushed at: 10 days ago - Stars: 42 - Forks: 1

Madhu-Krishnan-A-P/4bitadder

Verilog implementations of a 4-bit adder using behavioral, dataflow, and structural modeling styles, along with corresponding testbenches and block diagrams. This project demonstrates the design and simulation of digital adders as part of an academic lab experiment.

Language: Verilog - Size: 1.26 MB - Last synced at: 10 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

suryaturaga3142/chipdev-verilog

View my answers to HDL questions listed for practice on chipdev.

Language: SystemVerilog - Size: 13.7 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

shrine-maiden-heavy-industries/torii-hdl

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 1.2 GB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 17 - Forks: 1

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced at: 8 days ago - Pushed at: about 1 year ago - Stars: 349 - Forks: 83

m-labs/nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

Language: Python - Size: 1.3 MB - Last synced at: 6 days ago - Pushed at: over 3 years ago - Stars: 672 - Forks: 59

mattvenn/frequency_counter

Project 2.2 Frequency counter

Language: Verilog - Size: 52.7 KB - Last synced at: 1 day ago - Pushed at: 13 days ago - Stars: 11 - Forks: 7

mattvenn/rgb_mixer

Project 2.1 RGB Colour Mixer

Language: Python - Size: 137 KB - Last synced at: 1 day ago - Pushed at: 13 days ago - Stars: 4 - Forks: 14

briansune/Artix-Kintex-7-MIPI-DSI-4.5-inch-LCD

Artix or Kintex 7 MIPI DSI 4.5" LCD

Size: 5.78 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 1 - Forks: 0

stnolting/neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Language: VHDL - Size: 699 KB - Last synced at: 9 days ago - Pushed at: 10 days ago - Stars: 185 - Forks: 23

dbouche/fpga-pc-uart-comm

This demo allows to send and receive a byte from the PC to the FPGA and viceversa

Language: Verilog - Size: 42 KB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

briansune/Kintex-7-MIPI-DSI-5-inch-LCD

Size: 6.65 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 1 - Forks: 0

furrtek/SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

Language: Verilog - Size: 530 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 189 - Forks: 15

aappleby/metroboy

A repository of gate-level simulators and tools for the original Game Boy.

Language: C++ - Size: 72.8 MB - Last synced at: 14 days ago - Pushed at: 4 months ago - Stars: 1,139 - Forks: 36

masc-ucsc/livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Language: FIRRTL - Size: 114 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 223 - Forks: 51

SNRomon27/Combinational-Logic-Design-Using-Verilog-HDL

Basic combinational logic design using Verilog hardware description language (HDL). A step-by-step basic combinational logic design using built-in primitives. Used Vivado 2018.3 as a text editor and simulator.

Language: Verilog - Size: 136 KB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 0 - Forks: 0

briansune/Kintex-7-MIPI-DSI-6.9-inch-LCD

Size: 0 Bytes - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 0 - Forks: 0

spamegg1/reviews

Reviewing some online CS courses I took

Language: JavaScript - Size: 1.39 GB - Last synced at: 13 days ago - Pushed at: 3 months ago - Stars: 320 - Forks: 18

kactus2/kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Language: C++ - Size: 146 MB - Last synced at: 11 days ago - Pushed at: 13 days ago - Stars: 207 - Forks: 39

projectapheleia/avl

Apheleia Verification Library - Python based HDL verification library

Language: Python - Size: 0 Bytes - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 0 - Forks: 0

midimaster21b/rtl-core-library

A set of common RTL cores that I've developed over time and organized into a FuseSoC library.

Size: 25.4 KB - Last synced at: 18 days ago - Pushed at: 18 days ago - Stars: 7 - Forks: 1

1801BM1/cpu11

Revengineered ancient PDP-11 CPUs, originals and clones

Language: Verilog - Size: 31 MB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 159 - Forks: 25

KelvinChung2000/HDLGen

A simple Python HDL code generator for Verilog/SystemVerilog and VHDL.

Language: Python - Size: 57.6 KB - Last synced at: 20 days ago - Pushed at: 20 days ago - Stars: 2 - Forks: 1

briansune/Kintex-7-MIPI-DSI-3.4-inch-LCD

Kintex 7 MIPI DSI 3.4" LCD

Size: 2.63 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 2 - Forks: 0

somnath503/verilog-vending-machine

A Verilog HDL-based vending machine project using FSM and simulated in Xilinx Vivado.

Language: Verilog - Size: 134 KB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 1 - Forks: 0

f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Language: Jupyter Notebook - Size: 9.52 MB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 288 - Forks: 113

sigma-logic/hvtx

DVI/HDMITransmitter(Source) Core for Arora FPGA family

Language: SystemVerilog - Size: 124 KB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 3 - Forks: 0

sigma-logic/gowiners

Gowin EDA thin oxidized wrapper

Language: Rust - Size: 31.3 KB - Last synced at: 3 days ago - Pushed at: 22 days ago - Stars: 2 - Forks: 0

wierton/woop

Wierton's OoO processor. Implement ISA MIPS32 Release 1 and 2, can run linux (OoO features are under development).

Language: Scala - Size: 18.5 MB - Last synced at: 22 days ago - Pushed at: 22 days ago - Stars: 1 - Forks: 0

jasonyu1996/anvil

Language: OCaml - Size: 1.01 MB - Last synced at: 23 days ago - Pushed at: 23 days ago - Stars: 4 - Forks: 0

amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 3.75 MB - Last synced at: 23 days ago - Pushed at: 28 days ago - Stars: 1,694 - Forks: 178

analogdevicesinc/plutosdr-fw

PlutoSDR Firmware

Language: Shell - Size: 171 KB - Last synced at: 20 days ago - Pushed at: 8 months ago - Stars: 371 - Forks: 207

slaclab/surf

A huge VHDL library for FPGA and digital ASIC development

Language: VHDL - Size: 169 MB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 384 - Forks: 71

Hithaishisr/Router-1x3

A 1x3 packet router implemented in Verilog HDL, synthesized using Xilinx ISE with complete RTL and testbench support.

Language: Verilog - Size: 21.5 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 0 - Forks: 0

STARLORD-ugh/Kintex-7-MIPI-DSI-1.32-inch-LCD

Kintex 7 MIPI DSI 1.32" LCD

Size: 941 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 1 - Forks: 0

KoArtt/FPGA-TFT-MIPI-or-DPI

FPGA-TFT-MIPI-or-DPI

Size: 8.8 MB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 0 - Forks: 0

pku-liang/Cement

The Next-gen Language & Compiler Powering Efficient Hardware Design

Language: Rust - Size: 1.11 MB - Last synced at: 13 days ago - Pushed at: 5 months ago - Stars: 26 - Forks: 1

uio33/Kintex-7-MIPI-DSI-5.5-inch-4K-LCD

Kintex 7 MIPI DSI 5.5" 4K LCD

Size: 2.64 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 0 - Forks: 0

Lucasdk500/FPGA-LCD-MIPI-or-DPI

FPGA MIPI DSI

Size: 6.95 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 0 - Forks: 0

Laavaan-J/Kintex-7-MIPI-DSI-5.5-inch-2K-LCD

Kintex 7 MIPI DSI 5.5" 2K LCD

Size: 1.17 MB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 1 - Forks: 0

icarogabryel/cnn-accelerator

CNN accelerator using radix-4 Booth's algorithm described in VHDL . It multiplies a 32-bit integer with a 7-bit constant from a 3x3 kernel and accumulates the results.

Language: VHDL - Size: 245 KB - Last synced at: 5 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 0

Pconst167/sol-1

Sol-1: A CPU/Computer System made from 74 series logic.

Language: Assembly - Size: 507 MB - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 75 - Forks: 4

SymbiFlow/sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

Language: Python - Size: 17.4 MB - Last synced at: 2 days ago - Pushed at: over 4 years ago - Stars: 24 - Forks: 7

SymbiFlow/sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

Language: Python - Size: 153 KB - Last synced at: 22 days ago - Pushed at: over 1 year ago - Stars: 60 - Forks: 16

analogdevicesinc/m2k-fw

M2k firmware for the ADALM-2000 Active Learning Module

Language: Shell - Size: 187 KB - Last synced at: 24 days ago - Pushed at: 2 months ago - Stars: 60 - Forks: 28

infinitymdm/penguin

Digital hardware designs for flightless birds

Language: SystemVerilog - Size: 456 KB - Last synced at: 30 days ago - Pushed at: 30 days ago - Stars: 0 - Forks: 0

pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Language: Python - Size: 5.36 MB - Last synced at: 29 days ago - Pushed at: about 1 month ago - Stars: 411 - Forks: 50

cocotb/cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Language: Python - Size: 5.9 MB - Last synced at: 18 days ago - Pushed at: 8 months ago - Stars: 66 - Forks: 47

riskci/Artix-Kintex-7-MIPI-DSI-4.5-inch-LCD

The Artix-Kintex-7-MIPI-DSI-4.5-inch-LCD is a compact display module designed for embedded systems, featuring high-resolution visuals and low power consumption. It supports MIPI DSI interface, making it ideal for applications in mobile devices and portable electronics.

Size: 5.17 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0