HDLGen-ChatGPT/HDLGen-ChatGPT

HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

Language: Python - Size: 125 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 13 - Forks: 10

Katanta/IDATT2104-HDL

Repository exploring Hardware Description Languages through simple demos

Language: Verilog - Size: 636 KB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 2 - Forks: 0

analogdevicesinc/hdl

HDL libraries and projects

Language: Verilog - Size: 34.1 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 1,391 - Forks: 1,465

chryse-hdl/chryse

Project framework for Chisel

Language: Scala - Size: 133 KB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 1 - Forks: 0

amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 3.33 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 1,458 - Forks: 165

davidcastells/py4hw

Hardware Design/Visualization/Simulation/RTLGeneration Framework

Language: Jupyter Notebook - Size: 1.26 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 8 - Forks: 3

TinyTapeout/vga-playground

Playground for VGA projects on Tiny Tapeout

Language: JavaScript - Size: 1.32 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 0 - Forks: 0

blockwork-eda/blockwork

An opinionated build environment for EDA projects

Language: Python - Size: 680 KB - Last synced: 4 days ago - Pushed: 5 days ago - Stars: 12 - Forks: 1

codingonion/awesome-cuda-tensorrt-fpga

🔥🔥🔥 A collection of some awesome public NVIDIA CUDA, cuBLAS, cuDNN, TensorRT, AMD ROCm and FPGA projects.

Size: 40 KB - Last synced: 4 days ago - Pushed: 29 days ago - Stars: 93 - Forks: 11

2uger/tiny_soc

Simple implementation of SOC around PicoRV32 soft core.

Language: Verilog - Size: 31.3 KB - Last synced: 5 days ago - Pushed: 5 days ago - Stars: 1 - Forks: 0

algofoogle/anton1-tt03 Fork of TinyTapeout/tt03-verilog-demo

Anton's "Simple Multiply" submission for Tiny Tapeout 3 (TT03)

Language: Verilog - Size: 64.5 KB - Last synced: 5 days ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

Jacajack/hdl

A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding

Language: Rust - Size: 18.2 MB - Last synced: 6 days ago - Pushed: 6 days ago - Stars: 15 - Forks: 0

chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language: SystemVerilog - Size: 11 MB - Last synced: 6 days ago - Pushed: 6 days ago - Stars: 259 - Forks: 69

niqzart/PyloHD

High-level framework for simplification and systematization of processes in electronic design

Size: 894 KB - Last synced: 6 days ago - Pushed: 6 days ago - Stars: 0 - Forks: 0

kactus2/kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

Language: C++ - Size: 144 MB - Last synced: 6 days ago - Pushed: 6 days ago - Stars: 178 - Forks: 33

aappleby/metron

A C++ to Verilog translation tool with some basic guarantees that your code will work.

Language: C++ - Size: 83.8 MB - Last synced: 6 days ago - Pushed: 6 days ago - Stars: 150 - Forks: 12

aneels3/AES-128

Single pipeline AES 128 bit encryption using S-box as Look up table.

Language: Verilog - Size: 31.3 KB - Last synced: 7 days ago - Pushed: almost 6 years ago - Stars: 4 - Forks: 3

DFiantHDL/DFHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

Language: Scala - Size: 49.1 MB - Last synced: 6 days ago - Pushed: 7 days ago - Stars: 70 - Forks: 8

Mr-Bossman/KISC-V

KISCV, a KISS principle riscv32i CPU

Language: Verilog - Size: 1.38 MB - Last synced: 6 days ago - Pushed: 7 days ago - Stars: 21 - Forks: 1

bogdanvuk/pygears

HW Design: A Functional Approach

Language: Python - Size: 16.5 MB - Last synced: 5 days ago - Pushed: 11 months ago - Stars: 145 - Forks: 13

pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

Language: Python - Size: 5.4 MB - Last synced: 8 days ago - Pushed: 25 days ago - Stars: 353 - Forks: 44

shehanmunasinghe/tinyGPU

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

Language: SystemVerilog - Size: 1.23 MB - Last synced: 11 days ago - Pushed: almost 3 years ago - Stars: 25 - Forks: 7

ujjwal-2001/HDL-Bits-Solutions

This repo contains HDL-bits solutions

Language: Verilog - Size: 46.9 KB - Last synced: 12 days ago - Pushed: 13 days ago - Stars: 0 - Forks: 0

shrine-maiden-heavy-industries/torii-boards Fork of amaranth-lang/amaranth-boards

Torii HDL Board Definitions

Language: Python - Size: 45 MB - Last synced: 13 days ago - Pushed: 13 days ago - Stars: 0 - Forks: 0

sam210723/fpga

Collection of projects for various FPGA development boards

Language: Verilog - Size: 8.38 MB - Last synced: 13 days ago - Pushed: 13 days ago - Stars: 39 - Forks: 9

spamegg1/reviews

Reviewing some online CS courses I took

Language: JavaScript - Size: 1.39 GB - Last synced: 13 days ago - Pushed: 14 days ago - Stars: 267 - Forks: 18

slaclab/surf

A huge VHDL library for FPGA development

Language: VHDL - Size: 139 MB - Last synced: 16 days ago - Pushed: 17 days ago - Stars: 285 - Forks: 50

jfng/amaranth Fork of amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 26.7 MB - Last synced: 16 days ago - Pushed: 16 days ago - Stars: 0 - Forks: 0

SymbiFlow/sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

Language: Python - Size: 153 KB - Last synced: 9 days ago - Pushed: 8 months ago - Stars: 51 - Forks: 17

kivikakk/hdx 📦

[mirror] HDL development environment on Nix.

Language: Python - Size: 165 KB - Last synced: 7 days ago - Pushed: 22 days ago - Stars: 21 - Forks: 0

HDLGen-ChatGPT/PYNQ-SoC-Builder

This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.

Language: Python - Size: 18.6 MB - Last synced: 17 days ago - Pushed: 18 days ago - Stars: 1 - Forks: 1

XedaHQ/xeda

Cross EDA Abstraction and Automation

Language: Python - Size: 125 MB - Last synced: 20 days ago - Pushed: 21 days ago - Stars: 32 - Forks: 4

cdotrus/orbit

An HDL package manager.

Language: Rust - Size: 40.1 MB - Last synced: 25 days ago - Pushed: about 1 month ago - Stars: 14 - Forks: 1

rjoudrey/nand2tetris

My projects for the course

Language: Assembly - Size: 253 KB - Last synced: 22 days ago - Pushed: about 6 years ago - Stars: 0 - Forks: 0

nmarcopo/alteraMetronome

A metronome created with an Altera DE2-115 board and the hardware description language Verilog.

Language: Verilog - Size: 5.74 MB - Last synced: 23 days ago - Pushed: almost 6 years ago - Stars: 0 - Forks: 0

nmarcopo/alteraLaser

A variant on the classic "Breakout" video game, but the ball cuts through the bricks - like a laser!

Language: Verilog - Size: 10 MB - Last synced: 23 days ago - Pushed: almost 6 years ago - Stars: 1 - Forks: 0

0xvon/logical-gate

Language: Verilog - Size: 15.6 KB - Last synced: 23 days ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

josveji/Automatic-Parking-Access-Control

This project is a fully automated parking control system implemented using an HDL (Hardware Description Language), more specificaly Verilog. The system is designed to efficiently manage access of vehicles, requesting password and controlling the parking gate arm with the help of sensors.

Language: Verilog - Size: 52.7 KB - Last synced: 24 days ago - Pushed: 25 days ago - Stars: 0 - Forks: 0

cocotb/cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Language: Python - Size: 5.85 MB - Last synced: 24 days ago - Pushed: 3 months ago - Stars: 46 - Forks: 33

waasiq/hack-computer

Implementation of 16 Bit Computer

Language: Hack - Size: 784 KB - Last synced: 24 days ago - Pushed: 11 months ago - Stars: 0 - Forks: 0

GuzTech/shdl6800

shdl6800: A 6800 processor written in SpinalHDL

Language: Scala - Size: 114 KB - Last synced: 24 days ago - Pushed: over 4 years ago - Stars: 24 - Forks: 2

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced: 25 days ago - Pushed: 26 days ago - Stars: 205 - Forks: 67

JonathSpirit/ALUminium

ALUminium is a CPLD/FPGA code for a 8bits arithmetic–logic unit, made for processor like GP8B

Language: HTML - Size: 3.19 MB - Last synced: 25 days ago - Pushed: about 3 years ago - Stars: 1 - Forks: 0

raleighlittles/Applied_Digital_Logic_Exercises_Using_FPGAs

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

Language: Verilog - Size: 13.2 MB - Last synced: 25 days ago - Pushed: over 2 years ago - Stars: 8 - Forks: 1

mciepluc/cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

Language: Python - Size: 292 KB - Last synced: 23 days ago - Pushed: 6 months ago - Stars: 100 - Forks: 14

icglue/icglue

A Tcl-Library for scripted HDL generation

Language: Tcl - Size: 1.6 MB - Last synced: 26 days ago - Pushed: 26 days ago - Stars: 12 - Forks: 2

nand2tetris/web-ide

A web-based IDE for https://nand2tetris.org

Language: TypeScript - Size: 27.5 MB - Last synced: 29 days ago - Pushed: about 1 month ago - Stars: 18 - Forks: 8

google/pcbdl 📦

PCB Design Language: A programming way to design schematics.

Language: Python - Size: 6.12 MB - Last synced: 18 days ago - Pushed: about 3 years ago - Stars: 149 - Forks: 25

intel/rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

Language: Dart - Size: 16.9 MB - Last synced: 24 days ago - Pushed: about 1 month ago - Stars: 350 - Forks: 63

Pconst167/sol-1

Sol-1: A CPU/Computer System made from 74 series logic.

Language: C - Size: 351 MB - Last synced: 28 days ago - Pushed: 28 days ago - Stars: 59 - Forks: 2

Nicolesilvaa/Nand2Tetris

Repositório criado para armazenar as soluções dos projetos 01 e 02 do curso Nand2Tetris.

Language: Assembly - Size: 530 KB - Last synced: 30 days ago - Pushed: 30 days ago - Stars: 0 - Forks: 0

asyncvlsi/act

ACT hardware description language and core tools.

Language: C++ - Size: 4.77 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 92 - Forks: 22

vankxr/icyradio

Over-engineered SDR development board

Language: VHDL - Size: 388 MB - Last synced: 25 days ago - Pushed: about 1 month ago - Stars: 23 - Forks: 4

donn/Phi

Hardware description language that tries not to suck

Language: C++ - Size: 882 KB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 7 - Forks: 3

shyamal-anadkat/The-11-of-us

Language: SystemVerilog - Size: 5.1 MB - Last synced: about 1 month ago - Pushed: over 6 years ago - Stars: 2 - Forks: 0

Intuity/forastero

Making cocotb testbenches that bit easier

Language: Python - Size: 103 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 4 - Forks: 0

analogdevicesinc/HighSpeedConverterToolbox

MATLAB toolbox for ADI high speed converter products

Language: MATLAB - Size: 19.7 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 18 - Forks: 14

IlanIwumbwe/NandToTetris

Building the 16-bit computing system described in 'THE ELEMENTS OF COMPUTING SYSTEMS', written by Noam Nisan and Shimon Schocken.

Language: Hack - Size: 2.38 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

mLuby/logic-gates

A Hardware Description Language for logic gates interpreted by js

Language: JavaScript - Size: 3.91 KB - Last synced: about 1 month ago - Pushed: over 7 years ago - Stars: 1 - Forks: 0

FedericoSerafini/HLS-CNN

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

Language: C - Size: 21.6 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 22 - Forks: 5

SteffenReith/J1Sc

A reimplementation of a tiny stack CPU

Language: Scala - Size: 18.2 MB - Last synced: 24 days ago - Pushed: 6 months ago - Stars: 77 - Forks: 7

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

Language: Python - Size: 16.7 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 10 - Forks: 4

shrine-maiden-heavy-industries/torii-hdl Fork of amaranth-lang/amaranth

A modern hardware definition language and toolchain based on Python

Language: Python - Size: 751 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 9 - Forks: 4

langhuihui/monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

Language: Go - Size: 28.6 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1,356 - Forks: 222

wavedrom/vcd

Value Change Dump (VCD) parser

Language: JavaScript - Size: 374 KB - Last synced: 8 days ago - Pushed: 4 months ago - Stars: 33 - Forks: 9

f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Language: Jupyter Notebook - Size: 9.51 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 246 - Forks: 108

Nuand/bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

Language: VHDL - Size: 161 KB - Last synced: 28 days ago - Pushed: about 1 month ago - Stars: 369 - Forks: 48

tarsojabbes/loac

Roteiros desenvolvidos na disciplina de Laboratório de Organização e Arquitetura de Computadores no período 2022.2

Language: SystemVerilog - Size: 14.3 MB - Last synced: about 1 month ago - Pushed: 11 months ago - Stars: 0 - Forks: 0

Jai4/Nand-To-Tetris-

This Repo contains Projects implemented For this Course

Language: Assembly - Size: 104 KB - Last synced: about 1 month ago - Pushed: almost 7 years ago - Stars: 0 - Forks: 0

niedzielski/swankmania

Graphics processor and ACX705AKM LCD driver hardware implementation and misc.

Language: C - Size: 20.6 MB - Last synced: about 1 month ago - Pushed: over 11 years ago - Stars: 2 - Forks: 0

drom/awesome-hdl

Hardware Description Languages

Size: 128 KB - Last synced: about 1 month ago - Pushed: 2 months ago - Stars: 870 - Forks: 92

gateware-ts/gateware-ts

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Language: TypeScript - Size: 539 KB - Last synced: 20 days ago - Pushed: over 1 year ago - Stars: 98 - Forks: 6

kevinpt/symbolator

HDL symbol generator

Language: Python - Size: 407 KB - Last synced: 9 days ago - Pushed: over 1 year ago - Stars: 171 - Forks: 46

masc-ucsc/livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Language: Verilog - Size: 120 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 196 - Forks: 46

analogdevicesinc/plutosdr-fw

PlutoSDR Firmware

Language: Shell - Size: 156 KB - Last synced: about 1 month ago - Pushed: 4 months ago - Stars: 295 - Forks: 171

brianvhong/Assay-Development

Functional assays development for HDL and Plasma: Data analyses, visuals, reports

Language: HTML - Size: 3.39 MB - Last synced: about 1 month ago - Pushed: about 1 year ago - Stars: 2 - Forks: 0

YSawc/embassyFc2

developing NES on FPGA project.

Language: Rust - Size: 664 KB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 0 - Forks: 0

ichko/nand-to-tetris

This repository contains HWs and material from the nand to tetris course

Language: Assembly - Size: 873 KB - Last synced: about 1 month ago - Pushed: over 6 years ago - Stars: 1 - Forks: 1

smirnovich/smirnovich.github.io Fork of daattali/beautiful-jekyll

Build for a blog: https://smirnovich.github.io/

Language: HTML - Size: 5.07 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

aGhandhii/gb-apu

GameBoy Audio Processing Unit

Language: SystemVerilog - Size: 25.4 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

BrianHGinc/BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Language: SystemVerilog - Size: 9.94 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 64 - Forks: 28

pku-liang/Cement

A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.

Language: Rust - Size: 237 KB - Last synced: about 1 month ago - Pushed: 2 months ago - Stars: 4 - Forks: 0

balajirai/floating-point-multiplier

An efficient multi-format low-precision floating-point multiplier

Language: Verilog - Size: 440 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

WilsonChen003/HDLGen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Language: Verilog - Size: 21.1 MB - Last synced: about 1 month ago - Pushed: 7 months ago - Stars: 75 - Forks: 20

aappleby/metroboy

A repository of gate-level simulators and tools for the original Game Boy.

Language: C++ - Size: 72.8 MB - Last synced: about 1 month ago - Pushed: 3 months ago - Stars: 1,088 - Forks: 35

im-tomu/fomu-workshop

Support files for participating in a Fomu workshop

Language: Verilog - Size: 26.4 MB - Last synced: 25 days ago - Pushed: 2 months ago - Stars: 156 - Forks: 63

buhe/bugu-computer

💻 Build own computer by fpga.

Language: Verilog - Size: 319 KB - Last synced: 13 days ago - Pushed: almost 2 years ago - Stars: 23 - Forks: 2

Kitware/VeloView

VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.

Language: C++ - Size: 43.7 MB - Last synced: 17 days ago - Pushed: over 2 years ago - Stars: 313 - Forks: 168

yupferris/kaze 📦

An HDL embedded in Rust.

Language: Rust - Size: 319 KB - Last synced: about 1 month ago - Pushed: 6 months ago - Stars: 194 - Forks: 9

davidel/pyxhdl

Python Frontend For VHDL And Verilog

Language: VHDL - Size: 62.5 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 16 - Forks: 2

m-labs/nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

Language: Python - Size: 1.3 MB - Last synced: about 1 month ago - Pushed: over 2 years ago - Stars: 643 - Forks: 55

josnelihurt/fpga-stuff

Language: C - Size: 128 MB - Last synced: 2 months ago - Pushed: over 4 years ago - Stars: 2 - Forks: 1

GabbedT/ApogeoRV

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Language: SystemVerilog - Size: 7.03 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 12 - Forks: 1

joe-legg/Calcu-16

A small verilog processor.

Language: Verilog - Size: 4.74 MB - Last synced: 2 months ago - Pushed: over 5 years ago - Stars: 2 - Forks: 0

jiegec/fpu-wrappers

Wrappers for open source FPU hardware implementations.

Language: Verilog - Size: 2.3 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 27 - Forks: 4

sebport0/nand2tetris

My attempts at Element of Computer Systems/nand2tetris projects

Language: Scilab - Size: 16.6 KB - Last synced: 2 months ago - Pushed: about 4 years ago - Stars: 0 - Forks: 0

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.1 MB - Last synced: 2 months ago - Pushed: 11 months ago - Stars: 27 - Forks: 9

myriadrf/FreeSRP_GW

The FPGA design for the FreeSRP's Artix 7 FPGA

Language: C - Size: 3.47 MB - Last synced: 2 months ago - Pushed: about 7 years ago - Stars: 21 - Forks: 13

carlosedp/chisel-template

Chisel HDL Template Repository

Language: Scala - Size: 52.7 KB - Last synced: about 1 month ago - Pushed: over 1 year ago - Stars: 5 - Forks: 2

alialaei1/HDLab-FPGA-Development-Board

Open source FPGA development platform

Language: VHDL - Size: 21.6 MB - Last synced: 3 months ago - Pushed: 10 months ago - Stars: 46 - Forks: 22